Patents by Inventor Harumitsu Fujita

Harumitsu Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7518217
    Abstract: A semiconductor wafer is manufactured in such a way that a main surface of a semiconductor substrate is partitioned into a plurality of semiconductor element forming regions defined by scribing regions, wherein at least one pattern for measuring a width of a cut region and its positional shift is formed in proximity to a peripheral portion of the semiconductor substrate on a scribing line. The pattern is constituted by a plurality of micro patterns that are aligned in a reverse V-shape to traverse the scribing line and a pair of elongated patterns that partially overlap seal rings formed in both sides of the scribing line. It is possible to form a channel whose width is larger than the width of the cut region on the backside of the semiconductor substrate in correspondence with the scribing region in order to avoid the formation of chipping, cracks, and burrs during cutting.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: April 14, 2009
    Assignee: Yamaha Corporation
    Inventors: Harumitsu Fujita, Masaharu Sasaki
  • Patent number: 7193296
    Abstract: A semiconductor substrate is partitioned along scribing lines so as to form a plurality of IC regions encompassed by seal rings, wherein a passivation opening is formed in the scribing line in which a monitoring element is formed within a monitoring element region, which is encompassed by secondary seal rings, which are constituted by metal layers, oxidation layers and via holes. The secondary seal rings are formed to encompass the periphery of the monitoring element, which can thus precisely monitor characteristics of integrated circuits because it is possible to prevent water and impurities from infiltrating into the monitoring element region which is thus stabilized in characteristics.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: March 20, 2007
    Assignee: Yamaha Corporation
    Inventor: Harumitsu Fujita
  • Publication number: 20060113637
    Abstract: A semiconductor wafer is manufactured in such a way that a main surface of a semiconductor substrate is partitioned into a plurality of semiconductor element forming regions defined by scribing regions, wherein at least one pattern for measuring a width of a cut region and its positional shift is formed in proximity to a peripheral portion of the semiconductor substrate on a scribing line. The pattern is constituted by a plurality of micro patterns that are aligned in a reverse V-shape to traverse the scribing line and a pair of elongated patterns that partially overlap seal rings formed in both sides of the scribing line. It is possible to form a channel whose width is larger than the width of the cut region on the backside of the semiconductor substrate in correspondence with the scribing region in order to avoid the formation of chipping, cracks, and burrs during cutting.
    Type: Application
    Filed: November 9, 2005
    Publication date: June 1, 2006
    Inventors: Harumitsu Fujita, Masaharu Sasaki
  • Patent number: 7022574
    Abstract: In a semiconductor device comprising a MOS transistor driven at a relatively low voltage and a MOS transistor driven at a relatively high voltage formed on the same semiconductor substrate, the MOS transistor driven at the relatively high voltage comprises: a first active region of a first conductivity type in the semiconductor substrate; a first gate oxide film formed on the first active region and having increased thickness at the edge regions thereof than in the central region thereof in the direction of current flow; and a first electrode formed on the first gate oxide film and doped at a relatively low concentration with an impurity of a second conductivity type which is opposite to the first conductivity type; and the MOS transistor driven at the relatively low voltage comprises: a second active region of a first conductivity type in the semiconductor substrate; a second gate oxide film formed on the second active region; and a second electrode formed on the second gate oxide film and doped at a relativ
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: April 4, 2006
    Assignee: Yamaha Corporation
    Inventor: Harumitsu Fujita
  • Publication number: 20050184362
    Abstract: A semiconductor substrate is partitioned along scribing lines so as to form a plurality of IC regions encompassed by seal rings, wherein a passivation opening is formed in the scribing line in which a monitoring element is formed within a monitoring element region, which is encompassed by secondary seal rings, which are constituted by metal layers, oxidation layers and via holes. The secondary seal rings are formed to encompass the periphery of the monitoring element, which can thus Precisely monitor characteristics of integrated circuits because it is Possible to prevent water and impurities from infiltrating into the monitoring element region which is thus stabilized in characteristics.
    Type: Application
    Filed: January 24, 2005
    Publication date: August 25, 2005
    Inventor: Harumitsu Fujita
  • Publication number: 20010026983
    Abstract: In a semiconductor device comprising a MOS transistor driven at a relatively low voltage and a MOS transistor driven at a relatively high voltage formed on the same semiconductor substrate, the MOS transistor driven at the relatively high voltage comprises: a first active region of a first conductivity type in the semiconductor substrate; a first gate oxide film formed on the first active region and having increased thickness at the edge regions thereof than in the central region thereof in the direction of current flow; and a first electrode formed on the first gate oxide film and doped at a relatively low concentration with an impurity of a second conductivity type which is opposite to the first conductivity type; and the MOS transistor driven at the relatively low voltage comprises: a second active region of a first conductivity type in the semiconductor substrate; a second gate oxide film formed on the second active region; and a second electrode formed on the second gate oxide film and doped at a relativ
    Type: Application
    Filed: June 4, 2001
    Publication date: October 4, 2001
    Applicant: Yamaha Corporation
    Inventor: Harumitsu Fujita
  • Patent number: 6271572
    Abstract: In a semiconductor device comprising a MOS transistor driven at a relatively low voltage and a MOS transistor driven at a relatively high voltage formed on the same semiconductor substrate, the MOS transistor driven at the relatively high voltage comprises: a first active region of a first conductivity type in the semiconductor substrate; a first gate oxide film formed on the first active region and having increased thickness at the edge regions thereof than in the central region thereof in the direction of current flow; and a first electrode formed on the first gate oxide film and doped at a relatively low concentration with an impurity of a second conductivity type which is opposite to the first conductivity type; and the MOS transistor driven at the relatively low voltage comprises: a second active region of a first conductivity type in the semiconductor substrate; a second gate oxide film formed on the second active region; and a second electrode formed on the second gate oxide film and doped at a relativ
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: August 7, 2001
    Assignee: Yamaha Corporation
    Inventor: Harumitsu Fujita