Patents by Inventor Haruo Hyodo
Haruo Hyodo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6911353Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.Type: GrantFiled: May 2, 2002Date of Patent: June 28, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Tani, Takashi Sekibata, Haruo Hyodo
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Patent number: 6838765Abstract: The present invention comprises a first main face (22a) on a surface side of a substrate (21a). An island portion (26) is formed on the first main face (22a) and a semiconductor chip (29), etc. are adhered thereto. The semiconductor chip (29), etc. are sealed in the hollow portion that is constructed by a column portion (23) and a transparent glass plate (36). Then, the column portion (23) and the transparent glass plate (36) are adhered by epoxy resin, or the like.Type: GrantFiled: September 26, 2001Date of Patent: January 4, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Haruo Hyodo, Shigeo Kimura, Yasuhiro Takano
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Patent number: 6815808Abstract: The present invention comprises a first main face (22a) on the surface side of a substrate (21a). An island portion (26) is formed on the first main face (22a) and a semiconductor chip (29), etc. are adhered onto the first main face (22a). The semiconductor chip (29), etc. are sealed in a hollow space made by a column portion (23) and a transparent glass plate (36). Then, the column portion (23) and the glass plate (36) are adhered by the light-shielding adhesive resin made of epoxy resin. Accordingly, there can be provided the semiconductor device and a method of manufacturing the same, which can prevent the direct incidence of the light onto the semiconductor chip (29) and the degradation of the characteristic of the semiconductor chip (29) can be suppressed.Type: GrantFiled: September 26, 2001Date of Patent: November 9, 2004Assignee: Sanyo Electric, Co., Ltd.Inventors: Haruo Hyodo, Shigeo Kimura, Yasuhiro Takano
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Patent number: 6737285Abstract: The present invention provides a method for manufacturing a semiconductor device comprising steps of: bonding one semiconductor chip to each of multiple mounting portions of a substrate; covering the semiconductor chips bonded to the mounting portions with a common resin layer; bringing the substrate into contact with the resin layer and gluing the substrate to an adhesive sheet; and performing dicing and measurement for the semiconductor chips that are glued to the adhesive sheet.Type: GrantFiled: July 6, 2001Date of Patent: May 18, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Koji Iketani, Takayuki Tani, Takao Shibuya, Haruo Hyodo
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Patent number: 6451628Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor device which enables a decrease in mounting area on a printed circuit board and an increase in space efficiency on the printed circuit board.Type: GrantFiled: June 1, 2000Date of Patent: September 17, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Tani, Takao Shibuya, Haruo Hyodo
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Publication number: 20020119603Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.Type: ApplicationFiled: May 2, 2002Publication date: August 29, 2002Inventors: Takayuki Tani, Takashi Sekibata, Haruo Hyodo
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Patent number: 6410363Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.Type: GrantFiled: April 5, 2000Date of Patent: June 25, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Tani, Takashi Sekibata, Haruo Hyodo
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Publication number: 20020041038Abstract: The present invention comprises a first main face (22a) on a surface side of a substrate (21a). An island portion (26) is formed on the first main face (22a) and a semiconductor chip (29), etc. are adhered thereto. The semiconductor chip (29), etc. are sealed in the hollow portion that is constructed by a column portion (23) and a transparent glass plate (36). Then, the column portion (23) and the transparent glass plate (36) are adhered by epoxy resin, or the like.Type: ApplicationFiled: September 26, 2001Publication date: April 11, 2002Inventors: Haruo Hyodo, Shigeo Kimura, Yasuhiro Takano
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Publication number: 20020041016Abstract: The present invention comprises a first main face (22a) on the surface side of a substrate (21a) . An island portion (26) is formed on the first main face (22a) and a semiconductor chip (29), etc. are adhered onto the first main face (22a). The semiconductor chip (29), etc. are sealed in a hollow space made by a column portion (23) and a transparent glass plate (36). Then, the column portion (23) and the glass plate (36) are adhered by the light-shielding adhesive resin made of epoxy resin. Accordingly, there can be provided the semiconductor device and a method of manufacturing the same, which can prevent the direct incidence of the light onto the semiconductor chip (29) and the degradation of the characteristic of the semiconductor chip (29) can be suppressed.Type: ApplicationFiled: September 26, 2001Publication date: April 11, 2002Inventors: Haruo Hyodo, Shigeo Kimura, Yasuhiro Takano
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Publication number: 20020004250Abstract: The present invention provides a method for manufacturing a semiconductor device comprising steps of: bonding one semiconductor chip to each of multiple mounting portions of a substrate; covering the semiconductor chips bonded to the mounting portions with a common resin layer; bringing the substrate into contact with the resin layer and gluing the substrate to an adhesive sheet; and performing dicing and measurement for the semiconductor chips that are glued to the adhesive sheet.Type: ApplicationFiled: July 6, 2001Publication date: January 10, 2002Inventors: Koji Iketani, Takayuki Tani, Takao Shibuya, Haruo Hyodo
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Patent number: 6079852Abstract: An auxiliary light is provided with a housing having a light element in an inside thereof and an axially supporting portion in a side portion, and a bracket having a stand portion which is axially supported to the side portion of the housing by the axially supporting portion and a base portion which can be suitably supported to the vehicle. In this structure, a circular arc portion having a center of substantially center portion of the housing in a right and left direction is formed in both of the stand portion of the bracket and the axially supporting portion of the housing.Type: GrantFiled: June 5, 1997Date of Patent: June 27, 2000Assignee: PIAA CorporationInventors: Masashi Kamaya, Haruo Hyodo
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Patent number: 6080602Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor device which enables a decrease in mounting area on a printed circuit board and an increase in space efficiency on the printed circuit board.Type: GrantFiled: December 23, 1998Date of Patent: June 27, 2000Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Tani, Takao Shibuya, Haruo Hyodo
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Patent number: D574978Type: GrantFiled: October 25, 2007Date of Patent: August 12, 2008Assignee: PIAA CorporationInventors: Haruo Hyodo, Yukari Ishiwatari