Patents by Inventor Haruo Shimoda

Haruo Shimoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050221622
    Abstract: The present invention relates to a deposition method in which an insulating film that coats wirings mainly made of copper film and has low dielectric constant. Its constitution in the deposition method, where deposition gas is transformed into plasma and reaction is caused to form the insulating film having low dielectric constant, is that the deposition gas has a first silicon containing compound having cyclic siloxane bond and at least one of methyl group and methoxy group, and a second silicon containing organic compound having straight-chain siloxane bond and at least one of methyl group and methoxy group, as primary constituent gas.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 6, 2005
    Inventors: Yoshimi Shioya, Haruo Shimoda, Kazuo Maeda
  • Patent number: 4389967
    Abstract: In a boat with wheels for carrying semiconductor substrates, the friction surfaces of the wheel systems are coated with a silicon nitride film to prevent seizure from occurring during a diffusion, oxidation or annealing process for semiconductor substrates.
    Type: Grant
    Filed: January 11, 1981
    Date of Patent: June 28, 1983
    Assignee: Fujitsu Limited
    Inventors: Haruo Shimoda, Kaoru Tanabe
  • Patent number: 4210473
    Abstract: Disclosed is a process for producing a semiconductor device, especially, a high speed silicon gate field effect semiconductor device, by diffusing an impurity substance, such as arsenic or phosphorus, into a polycrystalline silicon layer to be converted into a silicon gate having a high electroconductivity and into portions of a single crystal silicon substrate to be converted into source and drain regions, in a sealed capsule, at an elevated temperature, under a vacuum. During the above-mentioned diffusing operation, the impurity substance can diffuse into the polycrystalline silicon layer at a higher diffusing speed than into the single crystal silicon substrate.
    Type: Grant
    Filed: October 30, 1978
    Date of Patent: July 1, 1980
    Assignee: Fujitsu Limited
    Inventors: Mikio Takagi, Hajime Kamioka, Haruo Shimoda, Hidekazu Miyamoto
  • Patent number: 3940288
    Abstract: A method of making a semiconductor device capable of high-speed operation is disclosed in which when the current gain-bandwidth is increased by the formation of a shallow base region. A side etching process is used to decrease the base spreading resistance and to allow ease in the formation of an emitter region of fine pattern. When the emitter region is formed by using polycrystalline silicon as a source of impurity diffusion, that area of an insulating film on a semiconductor substrate which adjoins the polycrystalline silicon is removed before the impurity diffusion so as to prevent an abnormal diffusion phenomenon.
    Type: Grant
    Filed: May 10, 1974
    Date of Patent: February 24, 1976
    Assignee: Fujitsu Limited
    Inventors: Mikio Takagi, Hajime Kamioka, Kazufumi Nakayama, Haruo Shimoda