Patents by Inventor Haruo Sunakawa

Haruo Sunakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220331813
    Abstract: A method of producing an inorganic material (S10) according to the present invention includes a vitrification step (S12) of applying shearing stress and compressive stress to a mixed powder (MP) of a plurality of kinds of inorganic compound powders by using a ring ball mill mechanism (70) to vitrify at least a part of the mixed powder (MP); and a dispersion step (S13) of dispersing the vitrified mixed powder (MP) after the vitrification step (S12), where a combined step of the vitrification step (S12) and the dispersion step (S13) is performed a plurality of times to obtain a vitrified inorganic material powder from the mixed powder.
    Type: Application
    Filed: June 11, 2020
    Publication date: October 20, 2022
    Applicant: FURUKAWA CO., LTD.
    Inventors: Yuichi Yaguchi, Yoshitaka Sakairi, Haruo Sunakawa
  • Publication number: 20180163323
    Abstract: A method for producing a group 13 nitride single crystal includes dissolving and crystal growing. The dissolving includes dissolving nitrogen in a mixed melt in a reaction vessel that contains the mixed melt, a seed crystal, and a surrounding member. The mixed melt contains an alkali metal and a group 13 metal. The seed crystal is a seed crystal that is placed in the mixed melt and includes a group 13 nitride crystal in which a principal face is a c-plane. The surrounding member is arranged so as to surround the entire area of a side face of the seed crystal. The crystal growing includes growing a group 13 nitride crystal on the seed crystal.
    Type: Application
    Filed: February 8, 2018
    Publication date: June 14, 2018
    Inventors: Takashi Satoh, Naoya Miyoshi, Junichi Wada, Masahiro Hayashi, Seiji Sarayama, Haruo Sunakawa, Yujirou Ishihara, Akira Usui
  • Patent number: 6809351
    Abstract: A Group III-V compound semiconductor epitaxial layer has a tilt angle of at most 100 seconds and/or a tilt angle of at most 100 seconds. The layer is epitaxially grown by use of a mask, wherein the mask satisfies the equation (1): h≧(w/2)tan &thgr;  (1) where “&thgr;” is a base angle of a facet structure of the Group III-V compound semiconductor layer on the epitaxial growth; “h” is a thickness of the mask; and “w” is an opening width of the mask at its lower level, and the opening width is defined in a direction included in a plane which is vertical to both the surface of the base layer and the side face of the facet structure.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: October 26, 2004
    Assignee: NEC Corporation
    Inventors: Masaru Kuramoto, Haruo Sunakawa
  • Publication number: 20030207125
    Abstract: After a GaN film 12 is formed on a (0001) plane sapphire (Al2O3) substrate 11, islands of the GaN film 12 are formed by wet etching. An upper part of the islands of the GaN film 12 is a single-crystal layer. By performing epitaxial growth over the islands of GaN film 12, a GaN film 15 with little crystal defect is obtained.
    Type: Application
    Filed: May 23, 2003
    Publication date: November 6, 2003
    Applicant: NEC CORPORATION
    Inventors: Haruo Sunakawa, Yoshishige Matsumoto, Akira Usui
  • Patent number: 6555845
    Abstract: The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures. As epitaxy is continued, adjacent facet structures come into contact so that the surface of the semiconductor layer becomes planarized. Since lattice defects extend towards the facet structures, they do not extend towards the surface of the semiconductor layer. Accordingly, the number of lattice defects in the vicinity of the semiconductor layer surface is reduced.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: April 29, 2003
    Assignee: NEC Corporation
    Inventors: Haruo Sunakawa, Akira Usui
  • Publication number: 20020168844
    Abstract: A Group III-V compound semiconductor epitaxial layer has a tilt angle of at most 100 seconds and/or a tilt angle of at most 100 seconds.
    Type: Application
    Filed: March 7, 2002
    Publication date: November 14, 2002
    Applicant: NEC CORPORATION
    Inventors: Masaru Kuramoto, Haruo Sunakawa
  • Publication number: 20020066403
    Abstract: The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 6, 2002
    Applicant: NEC CORPORATION
    Inventors: Haruo Sunakawa, Akira Usui
  • Patent number: 6348096
    Abstract: The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures. As epitaxy is continued, adjacent facet structures come into contact so that the surface of the semiconductor layer becomes planarized. Since lattice defects extend towards the facet structures, they do not extend towards the surface of the semiconductor layer. Accordingly, the number of lattice defects in the vicinity of the semiconductor layer surface is reduced.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: February 19, 2002
    Assignee: NEC Corporation
    Inventors: Haruo Sunakawa, Akira Usui
  • Publication number: 20010026950
    Abstract: In a method of manufacturing a semiconductor device by using a sapphire substrate, a nitrogen-based semiconductor thick film is deposited on the sapphire substrate by VPE and is left without any cracks by etching the sapphire substrate by an etchant. The nitrogen-based semiconductor thick film serves as a substrate for manufacturing the semiconductor device.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 4, 2001
    Applicant: NEC Corporation
    Inventors: Haruo Sunakawa, Akira Usui
  • Patent number: 6252261
    Abstract: A GaN crystal film having a mask patterned in a stripe for forming multiple growing areas on a sapphire substrate and coalesced GaN crystals covering the mask dividing the areas, grown from the neighboring growing areas, comprising defects where multiple dislocations along with the stripe are substantially aligned with the normal line of the substrate, in the crystal areas over the mask, and dislocations propagating in substantially parallel with the substrate surface while, in the vicinity of the areas where the crystals are coalesced over the mask, propagating substantially in the normal line of the substrate surface, and a manufacturing process therefor. According to this invention, there can be provided a GaN crystal film in which strain, defects and dislocations are reduced and which tends not to generate cracks.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: June 26, 2001
    Assignee: NEC Corporation
    Inventors: Akira Usui, Akira Sakai, Haruo Sunakawa, Masashi Mizuta, Yoshishige Matsumoto
  • Patent number: 6096130
    Abstract: A method of crystal growth of a GaN layer with an extremely high surface planarity over a GaAs substrate is provided, wherein a GaAs substrate is heated to a temperature in the range of 600.degree. C. to 700.degree. C. without supplying any group-V element including arsenic to form a Ga-rich surface on the GaAs substrate, before a first source material including N and a second source material including Ga are supplied along with a carrier gas onto a surface of the GaAs substrate to form a GaN layer over the GaAs substrate.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido
  • Patent number: 5843227
    Abstract: A crystal growth method for growing on a gallium arsenide (GaAs) substrate a gallium nitride (GaN) film which is good in surface flatness and superior in crystallinity. According to the method, a GaAs substrate having a surface which is inclined with respect to the GaAs(100) face is used. The inclination angle of the substrate surface is larger than 0 degree but smaller than 35 degrees with respect to the GaAs(100) face. The inclination direction of the substrate surface is within a range of an angular range from the ?0,0,1! direction of GaAs to the ?0,-1,0! direction past the ?0,-1,1! direction and angles less than 5 degrees on opposite sides of the angular range around an ?1,0,0! direction of gallium arsenide taken as an axis, or within another range crystallographically equivalent to the range. The GaN layer is formed on the surface of the GaAs substrate preferably by hydride vapor deposition method.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: December 1, 1998
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido, Atsushi Yamaguchi
  • Patent number: 5825053
    Abstract: In a heterostructure III-V nitride semiconductor device, an InP substrate has a surface having a sloped angle of 0.degree. to 16.degree. with respect to a (100) surface thereof. At least one GaN layer is formed on the InP substrate.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: October 20, 1998
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido, Atsushi Yamaguchi
  • Patent number: 4859627
    Abstract: A method of producing n-type III-V compound semiconductor comprises growing a plurality of monolayers of III-V compound semiconductor molecules on a III-V compound substrate; growing a single layer of group VI element on the III-V monolayers so as to occupy the lattice points for group V element by means of Atomic Layer Epitaxy process; decreasing the number of group VI element by exposing the single layer to the gas of group V element; and growing a plurality of monolayers of III-V compound semiconductor molecules on the group VI element-doped layer by means of the Atomic Layer Epitaxy process.
    Type: Grant
    Filed: July 1, 1988
    Date of Patent: August 22, 1989
    Assignee: NEC Corporation
    Inventor: Haruo Sunakawa
  • Patent number: 4845049
    Abstract: An n-type III-V compound semiconductor comprises a plurality of monolayers of III-V compound semiconductor molecules having a layer-by-layer structure of group III element and group V element laminated alternately, and a group VI element-doped monolayer. The group VI element-doped monolayer is inserted into the III-V compound semiconductor molecules by occupying lattice points which were occupied by the group V element. The layers of the semiconductor are grown by Atomic Layer Epitaxy process.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: July 4, 1989
    Assignee: NEC Corporation
    Inventor: Haruo Sunakawa