Patents by Inventor Harvey Ray
Harvey Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11016683Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.Type: GrantFiled: December 9, 2019Date of Patent: May 25, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Harvey Ray, Gary Gostin, Derek Alan Sherlock, Gregg B. Lesartre
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Patent number: 10735030Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.Type: GrantFiled: August 7, 2017Date of Patent: August 4, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen, Martin Foltin
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Patent number: 10664369Abstract: According to an example, a failed component in a fault-tolerant memory fabric may be determined by transmitting request packets along a plurality of routes between the redundancy controller and a media controller in periodic cycles. The redundancy controller may determine whether route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles. In response to determining that route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles, the media controller is established as failed. In response to determining that route failures for less than all of the plurality of routes have occurred within the number of consecutive periodic cycles, a fabric device is established as failed.Type: GrantFiled: January 30, 2015Date of Patent: May 26, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Derek Alan Sherlock, Harvey Ray, Michael Kontz
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Publication number: 20200117377Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.Type: ApplicationFiled: December 9, 2019Publication date: April 16, 2020Inventors: Harvey Ray, Gary Gostin, Derek Alan Sherlock, Gregg B. Lesartre
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Patent number: 10579519Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.Type: GrantFiled: July 30, 2015Date of Patent: March 3, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Mark David Lillibridge, Gary Gostin, Paolo Faraboschi, Derek Alan Sherlock, Harvey Ray
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Patent number: 10540109Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.Type: GrantFiled: September 2, 2014Date of Patent: January 21, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Harvey Ray, Gary Gostin, Derek Alan Sherlock, Gregg B. Lesartre
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Patent number: 10474389Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.Type: GrantFiled: July 5, 2016Date of Patent: November 12, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Brian S. Birk, Joseph F. Orth, Harvey Ray, Craig Warner
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Patent number: 10409681Abstract: According to an example, a retransmission sequence involving non-idempotent primitives in a fault-tolerant memory fabric may be modified. For example, a redundancy controller may request a sequence to access a stripe in the fault-tolerant memory fabric, wherein the sequence involves a non-idempotent primitive. In response to determining an expiration of a time threshold for the non-idempotent primitive, the redundancy controller may read other data in other cachelines in the stripe, calculate a new parity value by performing an idempotent exclusive-or primitive on the new data with the other data in the stripe, and write the new parity to the stripe using an idempotent write primitive.Type: GrantFiled: January 30, 2015Date of Patent: September 10, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Derek Alan Sherlock, Harvey Ray
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Patent number: 10402113Abstract: According to an example, hierarchal stripe locks may be obtained for a source stripe and a destination stripe. In response to receiving data for the source stripe, the data is written from the source stripe to the destination stripe, and the hierarchal stripe locks are released for the source stripe and the destination stripe. In response to receiving the data-migrated token, the hierarchal stripe locks are released for the source stripe and the destination stripe.Type: GrantFiled: July 31, 2014Date of Patent: September 3, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Harvey Ray, Derek Alan Sherlock, Gregg B. Lesartre
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Patent number: 10402287Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.Type: GrantFiled: January 30, 2015Date of Patent: September 3, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Derek Alan Sherlock, Harvey Ray, Chris Michael Brueggen
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Patent number: 10402261Abstract: An example device in accordance with an aspect of the present disclosure includes a redundancy controller and/or memory module to prevent data corruption and single point of failure in a fault-tolerant memory fabric. Devices include engines to issue and/or respond to primitive requests, identify failures and/or fault conditions, and receive and/or issue containment mode indications.Type: GrantFiled: March 31, 2015Date of Patent: September 3, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Derek Alan Sherlock, Harvey Ray
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Patent number: 10338965Abstract: In one example, a controller for managing a set of resources. A first structure has a first entry statically associated with one of the resources. A second structure has a second entry dynamically associative with one of the resources. A resource sharing mechanism borrows for the second structure an idle resource associated with the first structure.Type: GrantFiled: April 3, 2012Date of Patent: July 2, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Christopher Michael Brueggen, Harvey Ray, Derek Alan Sherlock
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Patent number: 10312943Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.Type: GrantFiled: March 24, 2017Date of Patent: June 4, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray
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Patent number: 10248571Abstract: In one example in accordance with the present disclosure, a system may include a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory and a location storer to store a rotation count of the rotation. The system may also include a data mover to move a cache line from the selected cache line address to a gap cache line address corresponding to the additional cache line address and a metadata setter to set a metadata of the gap cache line address to a value corresponding to the current rotation. The system may also include a current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event.Type: GrantFiled: August 11, 2016Date of Patent: April 2, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Harvey Ray
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Publication number: 20190065314Abstract: A memory device may operate in multiple modes. In a first mode, writes are not committed. In a second mode, writes are committed.Type: ApplicationFiled: March 22, 2016Publication date: February 28, 2019Inventors: Derek Alan Sherlock, Harvey Ray
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Publication number: 20190044546Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.Type: ApplicationFiled: August 7, 2017Publication date: February 7, 2019Inventors: Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen, Martin Foltin
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Publication number: 20180276068Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray
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Publication number: 20180217929Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.Type: ApplicationFiled: July 30, 2015Publication date: August 2, 2018Inventors: Mark David Lillibridge, Gary Gostin, Paolo Faraboschi, Derek Alan Sherlock, Harvey Ray
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Publication number: 20180046576Abstract: In one example in accordance with the present disclosure, a system may include a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory and a location storer to store a rotation count of the rotation. The system may also include a data mover to move a cache line from the selected cache line address to a gap cache line address corresponding to the additional cache line address and a metadata setter to set a metadata of the gap cache line address to a value corresponding to the current rotation. The system may also include a current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event.Type: ApplicationFiled: August 11, 2016Publication date: February 15, 2018Inventors: Gregg B. Lesartre, Harvey Ray
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Publication number: 20180011660Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.Type: ApplicationFiled: July 5, 2016Publication date: January 11, 2018Inventors: Gregg B. Lesartre, Brian S. Birk, Joseph F. Orth, Harvey Ray, Craig Warner