Abstract: The present invention relates to a device, the use thereof and a method for producing highly porous, crystalline surface coatings comprising at least two spraying devices operating in sequential sequence for applying coating agents from the storage vessels (3, 4) to a material arranged on a sample holder (1) and at least one rinsing device (5, 13, 16) for removing unbound molecules from the coated surface.

Abstract: Provided are graphene nanoribbons (GNRs), methods of making GNRs, and uses of the GNRs. The methods can provide control over GNR parameters such as, for example, length, width, and edge composition (e.g., edge functional groups). The methods are based on a metal catalyzed cycloaddition reaction at the carbon-carbon triple bonds of a poly(phenylene ethynylene) polymer. The GNRs can be used in devices such a microelectronic devices.

Abstract: The present invention relates to a device, the use thereof and a method for producing highly porous, crystalline surface coatings comprising at least two spraying devices operating in sequential sequence for applying coating agents from the storage vessels (3, 4) to a material arranged on a sample holder (1) and at least one rinsing device (5, 13, 16) for removing unbound molecules from the coated surface.

Abstract: Provided are graphene nanoribbons (GNRs), methods of making GNRs, and uses of the GNRs. The methods can provide control over GNR parameters such as, for example, length, width, and edge composition (e.g., edge functional groups). The methods are based on a metal catalyzed cycloaddition reaction at the carbon-carbon triple bonds of a poly(phenylene ethynylene) polymer. The GNRs can be used in devices such a microelectronic devices.

Abstract: A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.

Abstract: In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.

Abstract: Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.

Abstract: Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.