Abstract: Devices and related methods for the dynamic correction of spinal deformities are disclosed. The devices and methods are particularly useful for correcting an abnormal curvature of the spine. In one exemplary embodiment, a method for correcting deformity via a spinal implant that can include a polymer between or attached to a top and bottom plate, which can exist in a wedge-shaped configuration in order to apply asymmetric forces to the spinal column, is provided. The implant may be inserted between adjacent vertebrae comprising part of the abnormal curvature, thereby restoring the normal curvature of a spine.

Abstract: Devices and related methods for the dynamic correction of spinal deformities are disclosed. The devices and methods are particularly useful for correcting an abnormal curvature of the spine. In one exemplary embodiment, a method for correcting deformity via a spinal implant that can include a polymer between or attached to a top and bottom plate, which can exist in a wedge-shaped configuration in order to apply asymmetric forces to the spinal column, is provided. The implant may be inserted between adjacent vertebrae comprising part of the abnormal curvature, thereby restoring the normal curvature of a spine.

Abstract: Devices and related methods for the dynamic correction of spinal deformities are disclosed. The devices and methods are particularly useful for correcting an abnormal curvature of the spine. In one exemplary embodiment, a method for correcting deformity via a spinal implant that can include a polymer between or attached to a top and bottom plate, which can exist in a wedge-shaped configuration in order to apply asymmetric forces to the spinal column, is provided. The implant may be inserted between adjacent vertebrae comprising part of the abnormal curvature, thereby restoring the normal curvature of a spine.

Abstract: A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.

Abstract: A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.

Abstract: A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.

Abstract: A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.

Abstract: RFID systems are disclosed that include at least one RFID receiver system and a distributed exciter architecture. Exciters can be connected via wired and/or wireless connections to the RFID receiver system, which can control activation of the exciters to detect the presence of RFID tags within interrogation spaces defined by the exciter topology. One embodiment includes an RFID receiver system configured to detect information from RFID tags within a receive coverage area, and a plurality of exciters defining a plurality of interrogation spaces within the receive coverage area of the receiver system. The receiver system is configured to transmit a control signal that identifies one of the exciters and includes information indicative of an RFID tag interrogation signal, the exciters are configured to receive the control signal, and the exciter identified in the control signal is configured to illuminate an interrogation space with the RFID tag interrogation signal.

Abstract: RFID systems are disclosed that include at least one RFID receiver system and a distributed exciter architecture. The exciters can be connected via wired and/or wireless connections to the RFID receiver system and the RFID receiver system can control the activation of the exciters to detect the presence of RFID tags within interrogation spaces defined by the exciter topology. In several embodiments, the RFID receiver system performs location estimation to determine the interrogation space in which a specific RFID tag or collection of RFID tags is located. One embodiment of the invention includes an RFID receiver system configured to detect information from RFID tags within a receive coverage area, and a plurality of exciters defining a plurality of interrogation spaces within the receive coverage area of the RFID receiver system.

Abstract: A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure; test configuration circuitry for configuring any desired set of logic elements, interconnect structure and configuration latches during reset state that links the logic elements and interconnect structure to form a complete path between the interface points of the programmable logic device to enable testing of the desired elements in the complete path.

Abstract: RFID systems are disclosed that include at least one RFID receiver system and a distributed exciter architecture. The exciters can be connected via wired and/or wireless connections to the RFID receiver system and the RFID receiver system can control the activation of the exciters to detect the presence of RFID tags within interrogation spaces defined by the exciter topology. In several embodiments, the RFID receiver system performs location estimation to determine the interrogation space in which a specific RFID tag or collection of RFID tags is located. One embodiment of the invention includes an RFID receiver system configured to detect information from RFID tags within a receive coverage area, and a plurality of exciters defining a plurality of interrogation spaces within the receive coverage area of the RFID receiver system.

Abstract: An efficient Content Addressable Memory array for Classless Inter-Domain Routing with each CAM cell including an additional storage unit for storing the prefix length associated with the contents of the cell. An enabling logic connects the prefix length value to a wired OR plane common to all CAM cells, and a sequential bit wise comparison unit has its inputs connected to the wired OR plane and the additional storage unit with its output controlling the enabling logic.

Abstract: An improved Built-In-Self-Test (BIST) architecture for Content Addressable Memory (CAM) devices, including a bit scanner for reading out the contents of the matchlines of the CAM cells as a serial bit stream; a bit transition detector that detects and determines the address of each bit transition in the serial bit stream; a state machine that generates bit addresses for each expected transition in the serial bit stream; and an analyser that compares expected transition bit addresses with detected transition addresses and declares a BIST failure if expected and detected transition addresses do not match at any point in the bit stream.