Abstract: A non-volatile memory device including a substrate including a first area and a second area, a mold structure on the substrate, the mold structure including gate electrodes and mold insulating films alternately stacked on each other in a stepwise manner, an interlayer insulating film covering the mold structure, a channel structure on the first area, the channel structure extending through the mold structure and connected to the gate electrodes, and a through-contact on the second area and extending through the interlayer insulating film, the through-contact including a first portion in a first trench and a second portion in a second trench, the first portion including a liner film along a sidewall and a bottom surface of the first trench and a filling film on the liner film, wherein the filling film being a multi-grain conductive material, and the second portion being a single grain conductive material, may be provided.

Abstract: A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.

Abstract: A semiconductor device includes an insulating structure, a first conductive structure in the insulating structure, the first conductive structure including a first conductive layer and a second conductive layer, and a second conductive structure in the insulating structure, the second conductive structure including a first conductive layer of the second conductive structure. A width of the first conductive structure is larger than a width of the second conductive structure. The first conductive layer of the first conductive structure, the second conductive layer of the first conductive structure, and the first conductive layer of the second conductive structure include a same nonmetal element. A concentration of the nonmetal element in the second conductive layer of the first conductive structure is higher than a concentration of the nonmetal element in the first conductive layer of the first conductive structure and first conductive layer of the second conductive structure.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

Abstract: An electrode structure includes a conductive electrode, the conductive electrode including a first surface, an insulating layer on the conductive electrode, the insulating layer being in contact with the first surface of the conductive electrode, and a nano dot pattern in the conductive electrode and spaced apart from the first surface of the conductive electrode, the nano dot pattern including nano dots arranged in parallel to the first surface of the conductive electrode, and each of the nano dots including a first side surface adjacent to the first surface of the conductive electrode, the first side surface being flat and parallel to the first surface of the conductive electrode, and a second side surface opposite to the first side surface, the second side surface being convex in a direction away from the first surface of the conductive electrode.

Abstract: Semiconductor devices including a substrate including a cell array region and a through electrode region, an electrode stack on the substrate and including electrodes, vertical structures penetrating the electrode stack within the cell array region, vertical fence structures within an extension region and surrounding the through electrode region, and insulating layers being inside a perimeter defined by the vertical fence structures and being at the same level as the electrodes may be provided. The electrodes may include first protrusions protruding between the vertical fence structures in a plan view.

Abstract: A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

Abstract: A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

Abstract: Semiconductor devices including a substrate including a cell array region and a through electrode region, an electrode stack on the substrate and including electrodes, vertical structures penetrating the electrode stack within the cell array region, vertical fence structures within an extension region and surrounding the through electrode region, and insulating layers being inside a perimeter defined by the vertical fence structures and being at the same level as the electrodes may be provided. The electrodes may include first protrusions protruding between the vertical fence structures in a plan view.

Abstract: A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

Abstract: A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.