Patents by Inventor Hayato Goto

Hayato Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240138183
    Abstract: A method for manufacturing a novel display apparatus is provided. The method includes a first step of forming a first electrode, a second electrode, and a first gap over an insulating film, a second step of forming a first film over the second electrode; a third step of forming a first layer overlapping with the first electrode, a fourth step of removing the first film by an etching method to form a first unit overlapping with the first electrode, a fifth step of removing a surface of the second electrode, a sixth step of forming a second film over the first layer and the second electrode, a seventh step of forming a second layer overlapping with the second electrode, and an eighth step of removing the second film by an etching method using the second layer to form a second unit overlapping with the second electrode and a second gap.
    Type: Application
    Filed: September 27, 2023
    Publication date: April 25, 2024
    Inventors: Yasutaka NAKAZAWA, Takayuki OHIDE, Naoto GOTO, Hiroki ADACHI, Satoru IDOJIRI, Hayato YAMAWAKI, Kenichi OKAZAKI, Sachiko KAWAKAMI
  • Patent number: 11966450
    Abstract: According to an embodiment, a calculation device includes a memory and one or more processors configured to update, for elements each associated with first and second variables, the first and second variables for each unit time, sequentially for the unit times and alternately between the first and second variables. In a calculation process for each unit time, the one or more processors are configured to: for each of the elements, update the first variable based on the second variable; update the second variable based on the first variables of the elements; when the first variable is smaller than a first value, change the first variable to a value of the first value or more and a threshold value or less; and when the first variable is greater than a second value, change the first variable to a value of the threshold value or more and the second value or less.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 23, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hayato Goto
  • Patent number: 11941077
    Abstract: According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: March 26, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Goto, Kosuke Tatsumura
  • Publication number: 20240074122
    Abstract: A power semiconductor device includes a power module unit and a heat sink. An uneven portion is formed in a module base in the power module unit. The uneven portion includes a depression portion and a buffer depression portion. An uneven portion is formed in a heat sink base unit in the heat sink. The uneven portion and the uneven portion are fitted together by crimping so that the module base of the power module unit and a heat dissipation spreader of the heat sink are integrated. The buffer depression portion is left as a space.
    Type: Application
    Filed: January 14, 2022
    Publication date: February 29, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasuyuki SANDA, Masaki GOTO, Hayato TERADA, Hodaka ROKUBUICHI, Haruna TADA
  • Publication number: 20240037430
    Abstract: According to an embodiment, an information processing system solves a combinatorial optimization problem. The information processing system includes an Ising machine and a host unit. The Ising machine is hardware configured to perform a search process for searching for the ground state of an Ising model that represents the combinatorial optimization problem. The host unit is hardware connected to the Ising machine via an interface and configured to control the Ising machine. In the search process, for each of a plurality of Ising spins, the Ising machine alternately repeats an auxiliary variable update process for updating an auxiliary variable by a main variable and a main variable update process for updating the main variable by the auxiliary variable multiple times. Prior to the search process, the host unit transmits, to the Ising machine, an initial value of the auxiliary variable corresponding to each of the plurality of Ising spins.
    Type: Application
    Filed: October 9, 2023
    Publication date: February 1, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryo HIDAKA, Kosuke TATSUMURA, Masaya YAMASAKI, Yohei HAMAKAWA, Hayato GOTO
  • Publication number: 20240040599
    Abstract: According to one embodiment, a communication system includes a base station based on a communication standard and an allocation information generation device from the base station. The allocation information generation device comprises first and second generators. The first and the second generators output first and second allocation information until a first time elapses after an allocation request is received. The allocation information generation device transmits, to the base station, one of the first and the second allocation information which satisfies a constraint defined by the communication standard.
    Type: Application
    Filed: March 10, 2023
    Publication date: February 1, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Haruka OBATA, Toshihisa NABETANI, Kabuto ARAI, Kosuke TATSUMURA, Hayato GOTO, Yoshisato SAKAI
  • Publication number: 20240022236
    Abstract: According to one embodiment, an electronic circuit includes a band-pass filter, first circuits, a first port, and a second port. The band-pass filter includes filter resonators. Two adjacent filter resonators included in the filter resonators are mutually couplable. Each of the first circuits includes a first qubit and a first readout resonator. The first readout resonator is couplable with the first qubit. One of the filter resonators is couplable with the first readout resonator of one of the first circuits. Another one of the filter resonators is couplable with the first readout resonator of another one of the first circuits. The filter resonators include first, second, and third filter resonators. The first filter resonator is couplable with the first port. The second filter resonator is couplable with the second port. The third filter resonator is between the first filter resonator and the second filter resonator.
    Type: Application
    Filed: February 21, 2023
    Publication date: January 18, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noritsugu SHIOKAWA, Tamio KAWAGUCHI, Hayato GOTO, Taro KANAO, Yinghao HO
  • Publication number: 20240022235
    Abstract: According to one embodiment, an electronic circuit includes a band-pass filter, and at least one first circuit. The band-pass filter includes a plurality of filter resonators. Two adjacent filter resonators included in the filter resonators are mutually couplable. The first circuit includes a first qubit and a first readout resonator. The first readout resonator is couplable with the first qubit and one of the filter resonators. A passband of the band-pass filter includes a first passband and a second passband. A magnitude of a first ripple of the first passband is not more than 1/10 of a magnitude of a second ripple of the second passband.
    Type: Application
    Filed: February 14, 2023
    Publication date: January 18, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tamio KAWAGUCHI, Noritsugu SHIOKAWA, Hayato GOTO, Taro KANAO, Yinghao HO
  • Publication number: 20240013085
    Abstract: According to one embodiment, an electronic circuit includes a first qubit, a second qubit, a first coupler, a first readout conductive member, and a first filter. The first coupler includes a first resonator and a second resonator. The first resonator is couplable with the first qubit. The second resonator is couplable with the second qubit. The first filter includes a first filter portion, a first other-filter portion, and a first readout portion. The first filter portion is couplable with the first resonator. The first other-filter portion is couplable with the second resonator. The first readout portion is couplable with the first readout conductive member.
    Type: Application
    Filed: February 22, 2023
    Publication date: January 11, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato GOTO, Yinghao HO, Noritsugu SHIOKAWA, Tamio KAWAGUCHI
  • Publication number: 20240013076
    Abstract: A search device updates positions and momentums of a plurality of virtual particles, for each unit time from an initial time to an end time. The search device, for each unit time, calculates, for each of the particles, a position at a target time of a corresponding particle, calculates, for each of a plurality of nodes, a first accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to outgoing two or more directed edges, calculates, for each of the nodes, a second accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to incoming two or more directed edges, and calculates, for each of the particles, a momentum at the target time of a corresponding particle based on the first accumulative value and the second accumulative value.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kosuke TATSUMURA, Hayato GOTO, Masaya YAMASAKI, Ryo HIDAKA, Yoshisato SAKAI
  • Patent number: 11836458
    Abstract: According to one embodiment, a calculating device includes nonlinear oscillators, connectors, and a controller. One of the connectors connects at least two of the nonlinear oscillators. The nonlinear oscillators include first and second nonlinear oscillators. The first nonlinear oscillator includes a first circuit part and a first conductive member. The first circuit part includes first and second Josephson junctions. The second nonlinear oscillator includes a second circuit part and a second conductive member. The second circuit part includes third and fourth Josephson junctions. Numbers of the connectors connected to the first and second connectors are first and second numbers, respectively. The second number is greater than the first number. The controller performs at least a first operation of supplying a first signal to the first conductive member and supplying a second signal to the second conductive member. The second signal is different from the first signal.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: December 5, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taro Kanao, Hayato Goto
  • Patent number: 11816595
    Abstract: According to an embodiment, an information processing system solves a combinatorial optimization problem. The information processing system includes an Ising machine and a host unit. The Ising machine is hardware configured to perform a search process for searching for the ground state of an Ising model that represents the combinatorial optimization problem. The host unit is hardware connected to the Ising machine via an interface and configured to control the Ising machine. In the search process, for each of a plurality of Ising spins, the Ising machine alternately repeats an auxiliary variable update process for updating an auxiliary variable by a main variable and a main variable update process for updating the main variable by the auxiliary variable multiple times. Prior to the search process, the host unit transmits, to the Ising machine, an initial value of the auxiliary variable corresponding to each of the plurality of Ising spins.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 14, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryo Hidaka, Kosuke Tatsumura, Masaya Yamasaki, Yohei Hamakawa, Hayato Goto
  • Publication number: 20230353127
    Abstract: According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 2, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hayato GOTO
  • Patent number: 11803770
    Abstract: A search device updates positions and momentums of a plurality of virtual particles, for each unit time from an initial time to an end time. The search device, for each unit time, calculates, for each of the particles, a position at a target time of a corresponding particle, calculates, for each of a plurality of nodes, a first accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to outgoing two or more directed edges, calculates, for each of the nodes, a second accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to incoming two or more directed edges, and calculates, for each of the particles, a momentum at the target time of a corresponding particle based on the first accumulative value and the second accumulative value.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: October 31, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Hayato Goto, Masaya Yamasaki, Ryo Hidaka, Yoshisato Sakai
  • Publication number: 20230325467
    Abstract: A calculation apparatus according to an embodiment includes matrix multiplication circuitry, time evolution circuitry, management circuitry, and output circuitry. The matrix multiplication circuitry calculates N second intermediate variables at a first time point by matrix multiplication between N (N>=2) first intermediate variables at the first time point and a preset coefficient matrix in N rows and N columns. The time evolution circuitry calculates N first variables at a second time point and N first intermediate variables at the second time point, the second time point being a time point following one sampling period after the first time point. The management circuitry increments time point from a start time point for each sampling period and controls the above circuitry to perform a process for each time point. The output circuitry outputs N first variables at a preset end time point.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kosuke TATSUMURA, Hayato GOTO
  • Publication number: 20230281268
    Abstract: According to one embodiment, a calculation device includes a processing device configured to perform a processing procedure. The processing procedure includes a first update of a first vector, a second update of a second vector, and a third update of a third vector. The first update includes updating the first vector using the second vector and the third vector. The second update includes updating the second vector using the first vector. The processing device is configured to output at least one of the first vector obtained after repeating the processing procedure or a function of the first vector obtained after the repeating the processing procedure.
    Type: Application
    Filed: August 11, 2022
    Publication date: September 7, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshisato SAKAI, Hayato GOTO, Taro KANAO
  • Publication number: 20230281267
    Abstract: According to one embodiment, a calculation device includes a processing device configured to perform a processing procedure. The processing procedure includes a first update of a first vector, a second update of a second vector, and a third update of a third vector. The first update includes updating the first vector using the second vector and the third vector. The second update includes updating the second vector using the first vector. The processing device is configured to output an output of at least one of the first vector obtained after repeating the processing procedure or a function of the first vector obtained after the repeating the processing procedure.
    Type: Application
    Filed: August 10, 2022
    Publication date: September 7, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshisato SAKAI, Hayato GOTO, Taro KANAO
  • Patent number: 11741187
    Abstract: A calculation device includes a memory and one or more processors coupled to the memory and configured to alternately update, for elements each associated with first and second variables, the first and second variables, sequentially for unit times from an initial time to an end time. In an updating process for each unit time, the one or more processors are configured to: update, for each of the elements, the first variable based on the second variable; when the first variable is smaller than a first value, change the first variable to the first value and change the second variable to a third value; when the first variable is greater than a second value, change the first variable to the second value and change the second variable to the third value; and add an acceleration value calculated by a predetermined computation to the second variable.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 29, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taro Kanao, Hayato Goto, Ryo Hidaka, Kosuke Tatsumura
  • Patent number: 11742831
    Abstract: According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: August 29, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hayato Goto
  • Patent number: 11720645
    Abstract: A calculation apparatus according to an embodiment includes matrix multiplication circuitry, time evolution circuitry, management circuitry, and output circuitry. The matrix multiplication circuitry calculates N second intermediate variables at a first time point by matrix multiplication between N (N>=2) first intermediate variables at the first time point and a preset coefficient matrix in N rows and N columns. The time evolution circuitry calculates N first variables at a second time point and N first intermediate variables at the second time point, the second time point being a time point following one sampling period after the first time point. The management circuitry increments time point from a start time point for each sampling period and controls the above circuitry to perform a process for each time point. The output circuitry outputs N first variables at a preset end time point.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 8, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kosuke Tatsumura, Hayato Goto