Patents by Inventor Hayato Okuda
Hayato Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088582Abstract: A connector device has a constitution in a connector in which a plurality of terminals protrude into a connector opening. The plurality of terminals are respectively provided with a plurality of switches that have independent states of supplying power to the terminals and are switchable in between. A plurality of conductor plates are provided in the connector opening in an attachable and detachable state, and are each configured to electrically connect at least two of the plurality of terminals. The plurality of conductor plates are coupled by an insulating member.Type: ApplicationFiled: August 21, 2023Publication date: March 14, 2024Applicant: YAZAKI CORPORATIONInventors: Takahiko KATSURAMAKI, Hayato YAMAGUCHI, Sadaharu OKUDA
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Patent number: 9319128Abstract: A helicopter-mounted communication apparatus encodes video data at a compression rate based on a percentage of time a transmission beam is blocked by rotor blades. When a number of video packets is less than a specified number, the helicopter-mounted communication apparatus inserts null packets to keep a packet rate constant, then deletes the null packets and attaches additional information to another packet indicating the number of deleted null packets, and after buffering modulates and transmits a signal toward a communication satellite at transmittable-time points.Type: GrantFiled: March 18, 2013Date of Patent: April 19, 2016Assignee: Mitsubishi Electric CorporationInventors: Kazushi Yamamoto, Yutaka Ozaki, Hayato Okuda
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Publication number: 20150117303Abstract: A helicopter satellite communication system in which a terrestrial station communication apparatus communicates with a helicopter-mounted communication apparatus via a communication satellite. The terrestrial station communication apparatus includes: an encoder that performs error-correcting encoding of target transmission information; a packet interleaver that divides the encoded information into a plurality of packets and rearranges the packets; and a transmitter that transmits the rearranged packets to the helicopter-mounted communication apparatus. The helicopter-mounted communication apparatus includes: a receiver that receives the packets that are transmitted from the terrestrial station communication apparatus: a packet de-interleaver that rearranges the received packets in the original order; and a decoder that, by decoding the rearranged packets, restores the information that is lost due to the rotor blades of the helicopter.Type: ApplicationFiled: March 18, 2013Publication date: April 30, 2015Applicant: Mitsubishi Electric CorporationInventors: Kazushi Yamamoto, Yutaka Ozaki, Hayato Okuda
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Publication number: 20150055549Abstract: A helicopter-mounted communication apparatus encodes video data at a compression rate based on a percentage of time a transmission beam is blocked by rotor blades. When a number of video packets is less than a specified number, the helicopter-mounted communication apparatus inserts null packets to keep a packet rate constant, then deletes the null packets and attaches additional information to another packet indicating the number of deleted null packets, and after buffering modulates and transmits a signal toward a communication satellite at transmittable-time points.Type: ApplicationFiled: March 18, 2013Publication date: February 26, 2015Applicant: Mitsubishi Electric CorporationInventors: Kazushi Yamamoto, Yutaka Ozaki, Hayato Okuda
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Publication number: 20140170814Abstract: A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts.Type: ApplicationFiled: February 19, 2014Publication date: June 19, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hayato OKUDA, Yasunori KAWAOKA, Akira TAKASHIMA
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Publication number: 20140061887Abstract: A semiconductor device includes: a plurality of semiconductor chips to be mutually bonded via a bonding resin; a sealing resin to seal the plurality of semiconductor chips; and an anchor to be disposed in a first semiconductor chip included by the plurality of semiconductor chips and to seize the bonding resin.Type: ApplicationFiled: August 20, 2013Publication date: March 6, 2014Applicant: Fujitsu Semiconductor LimitedInventors: Hayato OKUDA, Yoshikazu KUMAGAYA
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Publication number: 20120104606Abstract: A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts.Type: ApplicationFiled: August 25, 2011Publication date: May 3, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hayato OKUDA, Yasunori Kawaoka, Akira Takashima
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Publication number: 20110239034Abstract: There is provided a transmission apparatus including: a clock generator; a first circuit including first data processors to process input data based on a first input clock, the first data processors electrically connected in series each transmitting data processed thereby and the first input clock to the next first data processor, the first input clock of the beginning first data processor being one of the clocks generated by the clock generator; a second circuit including: second data processors same as the first data processors; and phase adjusters each to adjust a phase of the second input clock and transmitting the second input clock adjusted thereby to the next second data processor; phase comparators each to compare phases of the first input clock and the second input clock; and a delay controller to control the phase adjusters, based on comparison results of the phase comparators.Type: ApplicationFiled: March 3, 2011Publication date: September 29, 2011Applicant: FUJITSU LIMITEDInventor: Hayato OKUDA
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Patent number: 7800421Abstract: An apparatus includes plural combinations of a clock supplier and a clock supply destination supplied with a clock from the clock supplier. The clock supply destination includes a return route through which the clock supply destination returns a clock to a corresponding clock supplier. The clock supplier includes a variable delay unit that adds a delay to the clock to be supplied to a corresponding clock supply destination; a comparison-reference-clock supply unit that supplies a comparison reference clock having the same phase as that of a comparison reference clock supplied from other clock supplier; a phase comparator that compares the phase of a return clock returned from a corresponding clock supply destination with that of the comparison reference clock; and a phase-difference control unit that controls the delay, so that the phases of the return clock and the comparison reference clock coincide with each other, based on the comparison result.Type: GrantFiled: November 27, 2007Date of Patent: September 21, 2010Assignee: Fujitsu LimitedInventors: Hayato Okuda, Hiroyuki Matsuo
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Publication number: 20080122503Abstract: An apparatus includes plural combinations of a clock supplier and a clock supply destination supplied with a clock from the clock supplier. The clock supply destination includes a return route through which the clock supply destination returns a clock to a corresponding clock supplier. The clock supplier includes a variable delay unit that adds a delay to the clock to be supplied to a corresponding clock supply destination; a comparison-reference-clock supply unit that supplies a comparison reference clock having the same phase as that of a comparison reference clock supplied from other clock supplier; a phase comparator that compares the phase of a return clock returned from a corresponding clock supply destination with that of the comparison reference clock; and a phase-difference control unit that controls the delay, so that the phases of the return clock and the comparison reference clock coincide with each other, based on the comparison result.Type: ApplicationFiled: November 27, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Hayato Okuda, Hiroyuki Matsuo
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Patent number: 6621169Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: August 29, 2001Date of Patent: September 16, 2003Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Publication number: 20020027295Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: August 29, 2001Publication date: March 7, 2002Applicant: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Patent number: 6316838Abstract: A semiconductor device includes a substrate provided with a plurality of leads, a face-down semiconductor element provided on one surface of the substrate, a first stacked semiconductor element and a second stacked semiconductor element provided on another surface of the substrate and connected to the substrate by wires, and an extended wiring mechanism for connecting electrodes of the face-down semiconductor element and electrodes of the first and second semiconductor elements. The connected electrodes are equi-electrodes whose electrical characteristics are equal.Type: GrantFiled: March 20, 2000Date of Patent: November 13, 2001Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Hayato Okuda, Tetsuya Hiraoka, Mitsutaka Sato, Yuji Akashi, Akira Okada, Masahiko Harayama
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Patent number: 6215182Abstract: A semiconductor device includes the first through third semiconductor devices which are stacked on a substrate and the first through third wires for connecting the semiconductor elements and the substrate. The first wires serve to connect electrodes of the first semiconductor element positioned uppermost and electrodes of the second semiconductor element. The second wires serve to connect the electrodes of the second semiconductor element and electrodes of the third semiconductor element. The third wires serve to connect the electrodes of the third semiconductor element and bonding pads of the substrate. Between the first wires and the electrodes of the second semiconductor element and between the second wires and the electrodes of the third semiconductor element, stud bumps are provided so as to form space therebetween, thereby avoiding short-circuits therebetween.Type: GrantFiled: March 20, 2000Date of Patent: April 10, 2001Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Hayato Okuda, Ryuji Nomoto, Yuji Akashi, Katsuro Hiraiwa
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Patent number: 5865496Abstract: A door structure of a motor vehicle has an inner panel and an outer panel. The door structure includes an impact load absorber member, provided at an outer panel side of the door, for absorbing and reducing a side collision impact load acting on a passenger by contact with the passenger. An opening is provided in the inner panel for allowing at least one portion of the impact load absorber member to enter. An passenger is compartment of the vehicle during a side collision. A supporting device is provided in the door for supporting the impact load absorber member.Type: GrantFiled: October 7, 1996Date of Patent: February 2, 1999Assignee: Mazda Motor CorporationInventors: Seiji Odan, Hayato Okuda, Kuniaki Ishigami