Abstract: Methods and apparatuses for adaptable receiver detection are provided. Embodiments include providing, by receiver detection circuitry at a transmitter coupled to a communication link, a voltage to the communication link; determining, by the receiver detection circuitry, a rise time corresponding to a rising edge change of the voltage on the communication link; determining, by the receiver detection circuitry, a fall time corresponding to a falling edge change of the voltage on the communication link; and determining, by the receiver detection circuitry, whether the rise time and the fall time are consistent with the transmitter being coupled through the communication link to a remote receiver.

Abstract: A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.

Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.

Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.

Abstract: A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.

Abstract: A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. Upon detecting an operating condition such as a temperature or power supply voltage level, the corresponding stored operational parameter is applied to the transmitter to control the frequency response.

Abstract: A design structure embodied in a machine-readable medium used in a design process provides a transmitter having a frequency response controllable in accordance with an operational parameter, and may include a storage operable to store operational parameters for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. A sensor can be used to detect an operating condition. In response to a change in the detected operating condition, a stored operational parameter corresponding to the detected operating condition can be used to control the frequency response of the transmitter.

Abstract: A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.

Abstract: A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.

Abstract: A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

Abstract: An apparatus is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating the additional information signals.

Abstract: A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

Abstract: Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

Abstract: A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is an average of a voltage signal transmitted by the transmitter and received by the receiver. The method further includes comparing the common-mode voltage of the transmitter with a common-mode voltage of the receiver. The method further includes maintaining the common-mode voltage of the receiver at a first level at which the common-mode voltage of the receiver substantially matches the common-mode voltage of the transmitter.