Patents by Inventor He-Gong Wei

He-Gong Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cascade analog-to-digital converting system
    Patent number: 8466823
    Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 18, 2013
    Assignee: University of Macau
    Inventors: U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
  • Delay generator
    Patent number: 8441295
    Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: May 14, 2013
    Assignee: University of Macau
    Inventors: He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
  • Time-interleaved pipelined-SAR analog to digital converter with low power consumption
    Patent number: 8427355
    Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 23, 2013
    Assignee: University of Macau
    Inventors: Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
  • DELAY GENERATOR
    Publication number: 20120286840
    Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.
    Type: Application
    Filed: November 4, 2011
    Publication date: November 15, 2012
    Applicant: University of Macau
    Inventors: He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
  • ANALOG TO DIGITAL CONVERTER CIRCUIT
    Publication number: 20120229313
    Abstract: The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic.
    Type: Application
    Filed: September 14, 2011
    Publication date: September 13, 2012
    Applicant: University of Macau
    Inventors: Sai-Weng SIN, He-Gong WEI, Franco MALOBERTI, Li DING, Yan ZHU, Chi-Hang CHAN, U-Fat CHIO, Seng-Pan U, Rui Paulo da Silva MARTINS
  • ANALOG-TO-DIGITAL CONVERTING SYSTEM
    Publication number: 20120194364
    Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
    Type: Application
    Filed: August 5, 2011
    Publication date: August 2, 2012
    Applicant: University of Macau
    Inventors: U-Fat CHIO, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti