Patents by Inventor He Ren
He Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220328352Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.Type: ApplicationFiled: June 18, 2022Publication date: October 13, 2022Applicant: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Mehul Naik
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Publication number: 20220285212Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Inventors: He REN, Hao JIANG, Shi YOU, Mehul B. NAIK
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Patent number: 11437274Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: GrantFiled: September 14, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Publication number: 20220270871Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.Type: ApplicationFiled: May 12, 2022Publication date: August 25, 2022Applicant: Applied Materials, Inc.Inventors: Xi Cen, Yakuan Yao, Yiming Lai, Kai Wu, Avgerinos V. Gelatos, David T. Or, Kevin Kashefi, Yu Lei, Lin Dong, He Ren, Yi Xu, Mehul Naik, Hao Chen, Mang-Mang Ling
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Patent number: 11410885Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.Type: GrantFiled: May 1, 2020Date of Patent: August 9, 2022Assignee: APPLIED MATERIALS, INC.Inventors: He Ren, Hao Jiang, Mehul Naik
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Patent number: 11380536Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.Type: GrantFiled: May 5, 2020Date of Patent: July 5, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Xi Cen, Yakuan Yao, Yiming Lai, Kai Wu, Avgerinos V. Gelatos, David T. Or, Kevin Kashefi, Yu Lei, Lin Dong, He Ren, Yi Xu, Mehul Naik, Hao Chen, Mang-Mang Ling
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Publication number: 20220181204Abstract: Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: Applied Materials, Inc.Inventors: Kevin Kashefi, Alexander Jansen, Mehul Naik, He Ren, Lu Chen, Feng Chen
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Publication number: 20220181201Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: Applied Materials, Inc.Inventors: Yi XU, Yufei HU, He REN, Yu LEI, Shi YOU, Kazuya DAITO
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Patent number: 11355391Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.Type: GrantFiled: February 27, 2020Date of Patent: June 7, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Xi Cen, Feiyue Ma, Kai Wu, Yu Lei, Kazuya Daito, Yi Xu, Vikash Banthia, Mei Chang, He Ren, Raymond Hoiman Hung, Yakuan Yao, Avgerinos V. Gelatos, David T. Or, Jing Zhou, Guoqiang Jian, Chi-Chou Lin, Yiming Lai, Jia Ye, Jenn-Yue Wang
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Publication number: 20220130676Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Applicant: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Mehul Naik, Wenting Hou, Jianxin Lei, Chen Gong, Yong Cao
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Patent number: 11289342Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.Type: GrantFiled: June 15, 2020Date of Patent: March 29, 2022Assignee: Applied Materials, Inc.Inventors: He Ren, Jong Mun Kim, Maximillian Clemons, Minrui Yu, Mehul Naik, Chentsau Ying
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Patent number: 11257677Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.Type: GrantFiled: January 24, 2020Date of Patent: February 22, 2022Assignee: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Mehul Naik, Wenting Hou, Jianxin Lei, Chen Gong, Yong Cao
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Patent number: 11205589Abstract: Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.Type: GrantFiled: October 6, 2019Date of Patent: December 21, 2021Assignee: APPLIED MATERIALS, INC.Inventors: He Ren, Hao Jiang, Mehul Naik, Srinivas D Nemani, Ellie Yieh
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Publication number: 20210384035Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a fluorine-free metallic tungsten film. The fluorine-free metallic tungsten film is exposed to a second process condition to deposit a tungsten film on the fluorine-free metallic tungsten film.Type: ApplicationFiled: April 8, 2021Publication date: December 9, 2021Applicant: Applied Materials, Inc.Inventors: Ilanit Fisher, Shih Chung Chen, Kedi Wu, Ashley Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Mandyam Sriram, Wen Ting Chen, Srinivas Gandikota, Chenfei Shen, Naomi Yoshida, He Ren
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Publication number: 20210384036Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.Type: ApplicationFiled: June 4, 2021Publication date: December 9, 2021Applicant: Applied Materials, Inc.Inventors: Ilanit Fisher, Chi-Chou Lin, Kedi Wu, Wen Ting Chen, Shih Chung Chen, Srinivas Gandikota, Mandyam Sriram, Chenfei Shen, Naomi Yoshida, He Ren
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Publication number: 20210351032Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.Type: ApplicationFiled: May 5, 2020Publication date: November 11, 2021Applicant: Applied Materials, Inc.Inventors: Xi Cen, Yakuan Yao, Yiming Lai, Kai Wu, Avgerinos V. Gelatos, David T. Or, Keyvan Kashefi, Yu Lei, Lin Dong, He Ren, Yi Xu, Mehul Naik, Hao Chen, Mang-Mang Ling
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Patent number: 11164780Abstract: Methods and apparatus for an interconnect formed on a substrate and a method of forming the interconnect thereon. In embodiments, the methods include etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom; removing the hard mask disposed atop the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.Type: GrantFiled: June 7, 2019Date of Patent: November 2, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Shi You, He Ren, Mehul Naik, Yi Xu, Feng Chen
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Publication number: 20210317580Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.Type: ApplicationFiled: April 14, 2020Publication date: October 14, 2021Inventors: Shi YOU, He REN, Naomi YOSHIDA, Nikolaos BEKIARIS, Mehul NAIK, Martin Jay SEAMONS, Jingmei LIANG, Mei-Yee SHEK
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Publication number: 20210305091Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Applicant: Micromaterials LLCInventors: He Ren, Amrita B. Mullick, Regina Freed, Mehul Naik, Uday Mitra
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Patent number: 11094588Abstract: Embodiments of the present disclosure generally relate an interconnect structure formed on a substrate and a method of forming the interconnect structure thereon. In one embodiment, a method of forming an interconnect structure includes forming an opening comprising a via and a trench in an insulating structure formed on a substrate, forming a first passivation layer in the opening, removing a portion of the first passivation layer from the opening, and selectively depositing a first metal containing material in the via.Type: GrantFiled: September 5, 2019Date of Patent: August 17, 2021Assignee: Applied Materials, Inc.Inventors: Shi You, He Ren, Mehul B. Naik