Patents by Inventor Hea Jong Yang
Hea Jong Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240159818Abstract: A reliability measuring apparatus includes an oxide-nitride-oxide-alumina (ONOA) current measuring circuit configured to measure an ONOA current by applying an ONOA current measuring voltage to a selected word line coupled to a selected memory cell in a flash memory and a reliability indicator generator configured to a reliability indicator using the ONOA current measured through the measuring circuit.Type: ApplicationFiled: November 2, 2023Publication date: May 16, 2024Applicant: SK hynix Inc.Inventors: Nam Cheol JEON, Hea Jong YANG, Tae Un YOUN
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Publication number: 20240021245Abstract: Provided herein is a memory device that may include a string, a voltage generation circuit, a page buffer, and a channel initializing circuit. The string may include select transistors and memory cells coupled in series between a bit line and a source line. The page buffer may be configured to precharge or discharge the bit line. The voltage generation circuit may be configured to apply a turn-on voltage or a turn-off voltage to select lines coupled to the select transistors, apply at least one operating voltage to word lines coupled to the memory cells, or discharge the select lines or the word lines. The channel initializing circuit may be configured to control the voltage generation circuit and the page buffer so as to initialize a channel of the string when an operation performed on the memory cells is completed or is suspended before being completed.Type: ApplicationFiled: November 25, 2022Publication date: January 18, 2024Applicant: SK hynix Inc.Inventors: Dong Jun KIM, Hea Jong YANG, Jong Wook KIM, Pyung Hwa KIM, Yong Hwan JANG
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Patent number: 10847226Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.Type: GrantFiled: December 13, 2018Date of Patent: November 24, 2020Assignee: SK hynix Inc.Inventors: Yong Jun Kim, Gae Hun Lee, Hea Jong Yang, Chan Lim, Min Kyu Jeong
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Publication number: 20190348121Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.Type: ApplicationFiled: December 13, 2018Publication date: November 14, 2019Applicant: SK hynix Inc.Inventors: Yong Jun KIM, Gae Hun LEE, Hea Jong YANG, Chan LIM, Min Kyu JEONG
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Patent number: 9349456Abstract: A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word lines of the memory cell block.Type: GrantFiled: May 30, 2012Date of Patent: May 24, 2016Assignee: SK Hynix Inc.Inventors: Se Jun Kim, Hea Jong Yang
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Publication number: 20140036598Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a select transistor, memory cells connected in serial and dummy memory cells disposed between the select transistor and the memory cells. A higher voltage is applied to a corresponding dummy memory cell as space between the corresponding dummy memory cell and the select to transistor is reduced in an erase operation.Type: ApplicationFiled: September 1, 2012Publication date: February 6, 2014Applicant: SK HYNIX INC.Inventor: Hea Jong YANG
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Patent number: 8537632Abstract: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.Type: GrantFiled: April 27, 2011Date of Patent: September 17, 2013Assignee: Hynix Semiconductor Inc.Inventors: Hea Jong Yang, Hee Youl Lee, Sung Jae Chung, Hyun Heo, Jeong Hyong Yi, Yong Dae Park
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Publication number: 20130159798Abstract: A non-volatile memory device and an operating method thereof are provided. The non-volatile memory device includes a memory unit including a plurality of memory blocks and a cam block, a peripheral circuit unit configured to program memory cells included in the plurality of memory blocks and the cam block or read programmed data, and a processor configured to control the peripheral circuit unit to measure an offset voltage by memory cell group in the plurality of memory blocks to set a read voltage during a test read operation and control the peripheral circuit unit to perform a read operation by memory cell group by using a new read voltage during a read operation.Type: ApplicationFiled: August 31, 2012Publication date: June 20, 2013Applicant: SK hynix Inc.Inventor: Hea Jong YANG
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Publication number: 20120307567Abstract: A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word lines of the memory cell block.Type: ApplicationFiled: May 30, 2012Publication date: December 6, 2012Inventors: Se Jun KIM, Hea Jong Yang
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Publication number: 20110261623Abstract: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.Type: ApplicationFiled: April 27, 2011Publication date: October 27, 2011Inventors: Hea Jong YANG, Hee Youl Lee, Sung Jae Chung, Hyun Heo, Jeong Hyong Yi, Yong Dae Park
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Patent number: 7630255Abstract: A method for erasing data of a NAND flash memory device including memory cell blocks may include using a first erase voltage applied to memory cells of a block to be erased. A first verification may be performed to verify erased states of the memory cells using a first verify voltage different than a second verify voltage. Memory cells that have not passed the first verification process are classified as a first group and a verification is performed on memory cells that have passed the first verification using the second verify voltage. Memory cells that have passed the second verification are classified as a second group and memory cells that have not passed the second verification are classified as a third group. Then data of the memory cells of the three groups are erased using first, second and third step voltages and first, second and third erase voltages, respectively.Type: GrantFiled: June 29, 2007Date of Patent: December 8, 2009Assignee: Hynix Semiconductor Inc.Inventor: Hea Jong Yang
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Publication number: 20080158994Abstract: A method for erasing data of a NAND flash memory device including memory cell blocks may include using a first erase voltage applied to memory cells of a block to be erased. A first verification may be performed to verify erased states of the memory cells using a first verify voltage different than a second verify voltage. Memory cells that have not passed the first verification process are classified as a first group and a verification is performed on memory cells that have passed the first verification using the second verify voltage. Memory cells that have passed the second verification are classified as a second group and memory cells that have not passed the second verification are classified as a third group. Then data of the memory cells of the three groups are erased using first, second and third step voltages and first, second and third erase voltages, respectively.Type: ApplicationFiled: June 29, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Hea Jong Yang