Abstract: A process for polishing a layer on a semiconductor wafer in which the incidence of undesirable scratches on the polished surface is reduced by using a multiple step polishing procedure. A relatively hard polishing pad is used first to planarize the wafer surface, using a chemically reactive and abrasive slurry. A second polishing step is then carried out on a relatively soft polishing pad, using a slurry to remove or reduce scratches introduced by polishing with the hard pad. A final polishing step is performed on the soft polishing pad using de-ionized water to remove particles from the surface of the wafer.

Abstract: A semiconductor and/or integrated circuit is provided having reduced particulate count upon or within the circuit. During power ramp down post etch or deposition, particles which formed within the plasma used to effectuate etch or deposition are gradually swept from the region above the integrated circuit. Plasma, and more specifically, the field which forms the plasma is maintained but at reduced levels to allow gradual reduction of particles through a multitude of steps. The steps culminate in eliminating power to the electrodes and plasma between the electrodes. However, at the time at which power is absent, only a few of the original particles remain in the critical region above the integrated circuit. Residual particles can be removed in a purge step following the successive sequence of ramp down steps. Gap between the electrodes is increased to a final position early in the ramp down sequence so that additional electrode movement does not occur when the field is weakened.