Abstract: The present invention relates to an organic light-emitting device employing, as a host of a light emission layer, an anthracene derivative compound having a characteristic structure by introduction of a benzofuran structure into the anthracene backbone, and as a dopant of the light emission layer, a polycyclic compound having a characteristic structure. The organic light-emitting device according to the present invention is an organic light-emitting device with significantly improved external quantum efficiency and can be advantageously utilized not only for lighting devices but also for various display devices, such as flat, flexible, and wearable displays.

Abstract: The present invention relates to: a pyrene derivative compound having a specific structure; and a high efficiency organic light-emitting device employing the pyrene derivative compound in a light emitting layer and thus having excellent light-emitting characteristics. The organic light-emitting device according to the present invention can be configured as a high efficiency organic light-emitting device having excellent light-emitting characteristics by employing the pyrene derivative compound having the specific structure as a host in the light emitting layer, and thus can be usefully applied industrially in lighting devices, as well as various display devices such as flat, flexible, and wearable displays.

Abstract: An organic light-emitting device according to the present invention uses a pyrene derivative compound having a characteristic structure as a host in a light-emitting layer to realize a long-lifespan and high-efficiency organic light-emitting device having excellent light-emitting characteristics in terms of lifespan and luminescence efficiency. Accordingly, the organic light-emitting device can be usefully applied, in the industrial aspect, for various display devices such as flat panel, flexible, and wearable displays, as well as lighting devices.

Abstract: Disclosed are a SiC MOSFET power semiconductor device and a method of manufacturing the same. More particularly, a SiC MOSFET power semiconductor device and a method of manufacturing the same are disclosed, including a trench gate having a hexagonal shape in a plan or layout view, to improve on-resistance (Rsp) characteristics and increase channel density.

Abstract: Disclosed are a semiconductor device (1) including a MOSPET region and an integrated diode region, and a manufacturing method thereof. More particularly, a semiconductor device (1) including a silicon carbide (SiC) MOSPET region and an integrated Schottky bather diode that reduce forward voltage drop (Vf), device area, and switching oscillation resulting from parasitic inductance are disclosed.

Abstract: The present invention relates to a novel heterocyclic compound usable in an organic light-emitting device and to an organic light-emitting device comprising same, wherein [chemical formula A] is as described in the detailed description of the invention.

Abstract: A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions.

Abstract: A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions.

Abstract: A high-voltage transistor may include a semiconductor substrate, and a gate electrode formed on and/or over the semiconductor substrate. Further, the high-voltage transistor may include source/drain regions formed on and/or over the semiconductor substrate at one side of the gate electrode, and impurity layers having a super junction structure and formed on and/or over a boundary of a drift region disposed below the gate electrode.

Abstract: Methods for manufacturing semiconductor devices simultaneously to implement low-voltage and high-voltage devices in a single chip. In one example embodiment, a method includes various acts. An isolation layer is formed on a wafer. A gate oxide layer and a lower gate poly are sequentially formed on a first low-voltage transistor region. A first poly oxide layer is formed. A nitride layer is formed on the first poly oxide layer. The nitride layer and the first poly oxide layer are etched. A field oxide layer is formed by selectively oxidizing portions exposed by the etching. A second poly oxide layer is formed. Gate patterns of each transistor region are completed by vapor-depositing an upper gate poly on a high-voltage transistor region, the first low-voltage transistor region and a second low-voltage transistor region. A source and drain region are formed.

Abstract: A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact plug, a first etch stop layer formed over the first insulating interlayer; a trench in the first insulating interlayer and the first etch stopper layer, a metal line in the trench, the metal line including a second contact plug projecting from the trench, wherein the metal line and the trench are formed as a single body, and a second insulating interlayer over the substrate including the metal line and the second contact plug.

Abstract: Methods for manufacturing semiconductor devices simultaneously to implement low-voltage and high-voltage devices in a single chip. In one example embodiment, a method includes various acts. An isolation layer is formed on a wafer. A gate oxide layer and a lower gate poly are sequentially formed on a first low-voltage transistor region. A first poly oxide layer is formed. A nitride layer is formed on the first poly oxide layer. The nitride layer and the first poly oxide layer are etched. A field oxide layer is formed by selectively oxidizing portions exposed by the etching. A second poly oxide layer is formed. Gate patterns of each transistor region are completed by vapor-depositing an upper gate poly on a high-voltage transistor region, the first low-voltage transistor region and a second low-voltage transistor region. A source and drain region are formed.

Abstract: A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact plug, a first etch stop layer formed over the first insulating interlayer; a trench in the first insulating interlayer and the first etch stopper layer, a metal line in the trench, the metal line including a second contact plug projecting from the trench, wherein the metal line and the trench are formed as a single body, and a second insulating interlayer over the substrate including the metal line and the second contact plug.