Abstract: A semiconductor memory device and a method for manufacturing a semiconductor memory device for increasing the coupling ratio are disclosed. In the memory device, a tunneling insulating film is formed on a semiconductor substrate. A floating gate is formed on the tunneling insulating film. A dielectric layer is formed on the surface of the floating gate. A control gate having a predetermined shape is formed on the dielectric layer. The capacitance between the control gate and the floating gate is increased, enlarging the coupling ratio. As a result, the power consumption can be reduced and the access time can be decreased.

Abstract: A flash memory device and fabrication method simplify the fabrication process of a semiconductor EEPROM device through a self-aligning process. The device includes a semiconductor substrate in which source and drain regions are defined, a first insulation layer formed on the semiconductor substrate, a first conductive layer pattern formed on a portion of the first insulation layer, sidewall spacers formed of a second conductive layer neighboring each sidewall of the first conductive layer pattern and covered by second and third insulation layers, and a third conductive layer pattern formed on the insulation layers and connected with the first conductive layer pattern.

Abstract: A flash memory device and fabrication method simplify the fabrication process of a semiconductor EEPROM device through a self-aligning process. The device includes a semiconductor substrate in which source and drain regions are defined, a first insulation layer formed on the semiconductor substrate, a first conductive layer pattern formed on a portion of the first insulation layer, sidewall spacers formed of a second conductive layer neighboring each sidewall of the first conductive layer pattern and covered by second and third insulation layers, and a third conductive layer pattern formed on the insulation layers and connected with the first conductive layer pattern.

Abstract: A memory device and a method of manufacturing the same in accordance with the present invention has an improved writing and erasing efficiency and an improved reliability. The memory device includes a first conductivity type substrate having second conductivity type source and drain regions spaced apart from each other. A source electrode having a T-shaped rail structure is formed in contact with the source region, and a drain electrode having a T-shaped rail structure is formed in contact with the drain region. An I-shaped floating gate is formed on the substrate between the source electrode and the drain electrode with a control gate formed on the floating gate.

Abstract: A semiconductor memory device and a method for manufacturing a semiconductor memory device for increasing the coupling ratio are disclosed. In the memory device, a tunneling insulating film is formed on a semiconductor substrate. A floating gate is formed on the tunneling insulating film. A dielectric layer is formed on the surface of the floating gate. A control gate having a predetermined shape is formed on the dielectric layer. The capacitance between the control gate and the floating gate is increased, enlarging the coupling ratio. As a result, the power consumption can be reduced and the access time can be decreased.

Abstract: A memory device and a method of manufacturing the same in accordance with the present invention has an improved writing and erasing efficiency and an improved reliability. The memory device includes a first conductivity type substrate having second conductivity type source and drain regions spaced apart from each other. A source electrode having a T-shaped rail structure is formed in contact with the source region, and a drain electrode having a T-shaped rail structure is formed in contact with the drain region. An I-shaped floating gate is formed on the substrate between the source electrode and the drain electrode with a control gate formed on the floating gate.