Abstract: A system selecting a process key factor in a commercial chemical process, includes: a data extraction unit that extracts tag data in units of a set period; an outlier discrimination unit that discriminates and aggregates outliers by tag by using an outlier extraction reference master; an outlier processing unit that generates an input mart draft excluding the outliers; a derived variable generation unit that generates derived variables for each tag, and generates an advanced input mart having the derived variable added thereto; a yield calculation unit that backs up the result of calculation of a yield by realizing a target value via exclusion and correction of the outliers; and a key factor extraction unit that extracts a yield key factor by calculating importance of each tag, and backs up importance data for each tag.

Abstract: A system for predicting process changes by using key factors in a commercial chemical process, includes: a key factor extraction and individual tag importance backup unit that extracts yield key factors by calculating the importance of each tag, and backs up importance data for each tag; and a yield prediction model training and yield prediction performing unit that performs yield prediction model training by using the importance of each tag accumulated in the key factor extraction and individual tag importance backup unit, and performs yield prediction so as to output a yield prediction result, evaluates performance, and selects an optimal prediction model.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A semiconductor system comprises a nonvolatile memory storing a patch code, the patch code comprising a unique identifier (ID). An internal read only memory (IROM) stores a boot code, the boot code comprising a patch code execution function for executing the patch code and a linked register (LR) address for specifying a storage location where the patch code is to be executed. A static random access memory (SRAM) stores a copy of the patch code at the storage location, the copy of the patch code including the unique ID. A processor executes the copy of the patch code from the storage location. The processor executes the copy of the patch code stored at the storage location in the SRAM according to the comparison result.

Abstract: A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data.

Abstract: A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A semiconductor system comprises a nonvolatile memory storing a patch code, the patch code comprising a unique identifier (ID). An internal read only memory (IROM) stores a boot code, the boot code comprising a patch code execution function for executing the patch code and a linked register (LR) address for specifying a storage location where the patch code is to be executed. A static random access memory (SRAM) stores a copy of the patch code at the storage location, the copy of the patch code including the unique ID. A processor executes the copy of the patch code from the storage location. The processor executes the copy of the patch code stored at the storage location in the SRAM according to the comparison result.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data.

Abstract: A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data.

Abstract: A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Abstract: A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value.

Abstract: A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data.