Abstract: A power supply system for an aircraft and a control method thereof are provided. The power supply system of the aircraft includes a fuel cell configured to generate electrical energy, a converter device configured to supply a voltage generated by the fuel cell to a first motor device for driving the aircraft through a first output terminal and switch a connection with the fuel cell depending on a predetermined driving mode, a battery configured to supply the voltage to a second motor device for driving the aircraft through a second output terminal, the second output terminal being connected with an output node of the fuel cell, and a processor configure to control a connection between the fuel cell and the converter device depending on the driving mode.

Abstract: The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer.

Abstract: The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer.

Abstract: A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and the floating gate. Therefore, inter-cell interference can be reduced without lowering program speed.

Abstract: The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer.

Abstract: A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.

Abstract: A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and the floating gate. Therefore, inter-cell interference can be reduced without lowering program speed.

Abstract: A method of manufacturing a non-volatile memory device includes providing a floating gate layer over a semiconductor substrate. The floating gate layer and the semiconductor substrate are etched to form a trench. An isolation structure is formed in the trench. An upper portion of the isolation structure is etched, wherein an upper sidewall of the floating gate layer is exposed by the etching of the upper portion of the isolation structure. An oxide layer is formed on the floating gate layer to round an upper corner of the floating gate layer. A control gate layer is formed over the floating gate layer.

Abstract: A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.

Abstract: Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and t

Abstract: Disclosed are a contact plug in a semiconductor device and method of forming the same. After a junction region where a contact plug is formed upwardly up to the bottom of a metal wire, the raised junction region and the metal wire are connected by a contact plug. Or after a first contact plug of the same area is formed on the junction region up to the bottom of the metal wires, the first contact plug is connected by a second contact plug. Thus, the width of the contact plug except for some portions is increased by maximum. It is thus possible to prevent an electric field from being concentrated and prohibit on-current from reduced, thus improving the electrical properties of devices.

Abstract: Provided is a high voltage transistor in a flash memory device comprising: a source/drain junction of a DDD structure consisting of a high-concentration impurity region and a low-concentration impurity region surrounding the high-concentration impurity region, the high-concentration impurity region being formed in parallel with a gate electrode at a distance spaced by a location in which a contact hole is formed, and having a rectangular shape whose width is the same as or wider than that of the contact hole and whose length is the same as or narrower than that of an active region through which the gate electrode passes. Accordingly, a current density to pass the gate electrode neighboring the contact hole portion and a current density to pass the gate electrode at a portion where the contact hole cannot be formed become uniform. A uniform and constant saturation current can be obtained regardless of the number of the contact hole.

Abstract: There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that expensive photograph equipments are required and the manufacturing costs are thus increased when defining a floating gate and a control gate in a flash memory cell used in a high-integration flash memory device, the present invention performs an etching process for defining a floating gate with an-isotropic etching process. Therefore, it can minimize the areas of a cell and thus obtain a high-integration device.

Abstract: Methods of erasing a flash memory device are disclosed. After performing a first erasure operation, the methods perform a second erasure operation wherein an erasure pulse width or an erasure voltage is increased if the number of erased cells is below a predetermined number of erased cells, and wherein an erasure pulse width or an erasure voltage is reduced if the number of erased cell is more than a predetermined number of erased cells.

Abstract: The invention relates to a flash EEPROM cell and method of manufacturing the same.

Abstract: Methods of erasing a flash memory device are disclosed. After performing a first erasure operation, the methods perform a second erasure operation wherein an erasure pulse width or an erasure voltage is increased if the number of erased cells is below a predetermined number of erased cells, and wherein an erasure pulse width or an erasure voltage is reduced if the number of erased cell is more than a predetermined number of erased cells.

Abstract: The invention relates to a flash EEPROM cell and method of manufacturing the same.