Abstract: A method for controlling a vehicle includes: determining an accelerator position sensor/brake pedal position sensor (APS/BPS) command value based on a state variable and a reward variable including a prediction value for a future velocity of the vehicle predicted based on a past APS/BPS command value of the vehicle; and learning for a reward value according to the reward variable to satisfy a predetermined goal based on a change that the determined APS/BPS command value causes to at least one state variable under given environment information.

Abstract: The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. The voltage generator generates a reference voltage signal having a substantially constant voltage level regardless of the variation in temperature. The temperature code generator compares a voltage level of the temperature voltage signal with a voltage level of the reference voltage signal to generate a plurality of temperature code signals including information on the variation in temperature based on the comparison.

Abstract: The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. The voltage generator generates a reference voltage signal having a substantially constant voltage level regardless of the variation in temperature. The temperature code generator compares a voltage level of the temperature voltage signal with a voltage level of the reference voltage signal to generate a plurality of temperature code signals including information on the variation in temperature based on the comparison.

Abstract: The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. The voltage generator generates a reference voltage signal having a substantially constant voltage level regardless of the variation in temperature. The temperature code generator compares a voltage level of the temperature voltage signal with a voltage level of the reference voltage signal to generate a plurality of temperature code signals including information on the variation in temperature based on the comparison.

Abstract: A semiconductor apparatus includes a first memory bank configured to store data transmitted through a first data line; and a precharge block configured to precharge the first data line to a level of a first voltage or a second voltage.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller receives a temperature code signal and responsively generates a mode set signal operable to adjust a level variation and a voltage variation rate of a temperature voltage signal, wherein the temperature voltage signal level varies according to temperature when a logic level combination of the temperature code signal is different from a predefined logic level combination. The semiconductor device generates the temperature voltage signal from a drivability and a resistance value set by the mode set signal. The semiconductor device generates the temperature code signal based on a comparison of the temperature voltage signal and a reference voltage signal.

Abstract: A semiconductor apparatus includes a first memory bank configured to store data transmitted through a first data line; and a precharge block configured to precharge the first data line to a level of a first voltage or a second voltage.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller receives a temperature code signal and responsively generates a mode set signal operable to adjust a level variation and a voltage variation rate of a temperature voltage signal, wherein the temperature voltage signal level varies according to temperature when a logic level combination of the temperature code signal is different from a predefined logic level combination. The semiconductor device generates the temperature voltage signal from a drivability and a resistance value set by the mode set signal. The semiconductor device generates the temperature code signal based on a comparison of the temperature voltage signal and a reference voltage signal.

Abstract: The temperature sensor includes a voltage generator and a temperature code generator. The voltage generator includes a first temperature element having a first resistance value and a second temperature element having a second resistance value and utilizes the first and second temperature elements to generate a temperature voltage signal having a voltage level that varies according to a variation in temperature. The voltage generator generates a reference voltage signal having a substantially constant voltage level regardless of the variation in temperature. The temperature code generator compares a voltage level of the temperature voltage signal with a voltage level of the reference voltage signal to generate a plurality of temperature code signals including information on the variation in temperature based on the comparison.

Abstract: Temperature sensors are provided. The temperature sensor includes a comparison voltage generator and a temperature voltage generator. The comparison voltage generator generates a first comparison voltage signal whose level varies according to temperature variation and a second comparison voltage signal whose level is constant regardless of temperature variation. The temperature voltage generator generates a first internal current signal whose level varies according to a level of the first comparison voltage signal and a second internal current signal whose level varies according to a level of the second comparison voltage signal. Further, the temperature voltage generator amplifies a current difference between the first and second internal current signals to generate a temperature voltage signal.

Abstract: Disclosed is a semiconductor memory device, including a plurality of internal voltage generation units configured to be enabled in response to each of a plurality of decoding signals and to generate an internal voltage, a controller configured to generate a plurality of control signals in response to a power up signal and a test mode signal, and a decoder configured to generate the plurality of decoding signals corresponding to at least one decoding source signal and to simultaneously activate some or all of the plurality of decoding signals in response to the control signals.

Abstract: A memory device includes a nonvolatile memory, operated by using a plurality of voltages and configured to output stored repair information in response to a boot-up signal, a plurality of registers configured to store the repair information output from the nonvolatile memory, a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers, and a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages.

Abstract: A semiconductor integrated circuit includes first and second bank groups, a first internal voltage control unit configured to generate a first enable pulse which is enabled when a first read operation or a first write operation is performed for banks included in the first bank group, and a first internal voltage generation unit configured to generate and supply a first internal voltage to the first bank group in response to the first enable pulse, wherein an enable period of the first enable pulse is set to be longer in the first write operation than in the first read operation.

Abstract: Disclosed is a semiconductor memory device, including a plurality of internal voltage generation units configured to be enabled in response to each of a plurality of decoding signals and to generate an internal voltage, a controller configured to generate a plurality of control signals in response to a power up signal and a test mode signal, and a decoder configured to generate the plurality of decoding signals corresponding to at least one decoding source signal and to simultaneously activate some or all of the plurality of decoding signals in response to the control signals.

Abstract: A semiconductor integrated circuit includes first and second bank groups, a first internal voltage control unit configured to generate a first enable pulse which is enabled when a first read operation or a first write operation is performed for banks included in the first bank group, and a first internal voltage generation unit configured to generate and supply a first internal voltage to the first bank group in response to the first enable pulse, wherein an enable period of the first enable pulse is set to be longer in the first write operation than in the first read operation.