Patents by Inventor Hee Joong Suh

Hee Joong Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip stack-type semiconductor package and method for fabricating the same
    Patent number: 6528353
    Abstract: Chip stack type semiconductor package and method for fabricating the same, the package including a lower chip having a center pad formation surface defined at a bottom thereof, an upper chip stacked on the lower chip by being adhered to a top surface of the lower chip having no center pad formed thereon and having a center pad formation surface defined at a top surface thereof, both surface adhesive insulating tapes attached on regions spaced from, and positioned left and right sides of respective center pads formed in the center pad formation surfaces of the lower chip and the upper chip, leads having inner lead portions inside of a molded body of an encapsulation resin and outer lead portions exposed outside of the molded body and both end portions of the leads attached to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the upper chip and to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the lower chip oppos
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: March 4, 2003
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Hee Joong Suh, Bog Kyou Lee
  • Ultra high density integrated circuit BLP stack and method for fabricating the same
    Patent number: 6399420
    Abstract: BLP stack is disclosed which has a higher reliability and a less area of mounting for providing a denser package, including a first package having external power connection leads each started to be exposed through a bottom thereof and extended to a top surface through a side surface inclusive of bottom lead portions on a bottom surface, side lead portions on a side surface, and upper lead portions on a top surface, and a second package having external power connection leads started to be exposed through a bottom thereof and brought into contact with the external power connection leads on the first package to be electrically connected thereto.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: June 4, 2002
    Assignee: LG Semicon Co., Ltd.
    Inventors: Gi Bon Cha, Hee Joong Suh, Chang Kuk Choi
  • Ultra high density integrated circuit BLP stack and method for fabricating the same
    Publication number: 20010040278
    Abstract: BLP stack is disclosed which has a higher reliability and a less area of mounting for providing a denser package, including a first package having external power connection leads each started to be exposed through a bottom thereof and extended to a top surface through a side surface inclusive of bottom lead portions on a bottom surface, side lead portions on a side surface, and upper lead portions on a top surface, and a second package having external power connection leads started to be exposed through a bottom thereof and brought into contact with the external power connection leads on the first package to be electrically connected thereto.
    Type: Application
    Filed: May 4, 2001
    Publication date: November 15, 2001
    Applicant: LG SEMICON CO., LTD.
    Inventors: Gi Bon Cha, Hee Joong Suh, Chang Kuk Choi
  • Chip stack-type semiconductor package and method for fabricating the same
    Publication number: 20010000053
    Abstract: Chip stack type semiconductor package and method for fabricating the same, the package including a lower chip having a center pad formation surface defined at a bottom thereof, an upper chip stacked on the lower chip by being adhered to a top surface of the lower chip having no center pad formed thereon and having a center pad formation surface defined at a top surface thereof, both surface adhesive insulating tapes attached on regions spaced from, and positioned left and right sides of respective center pads formed in the center pad formation surfaces of the lower chip and the upper chip, leads having inner lead portions inside of a molded body of an encapsulation resin and outer lead portions exposed outside of the molded body and both end portions of the leads attached to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the upper chip and to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the lower chip oppos
    Type: Application
    Filed: December 4, 2000
    Publication date: March 22, 2001
    Inventors: Hee Joong Suh, Bog Kyou Lee
  • Chip stack-type semiconductor package and method for fabricating the same
    Patent number: 6177721
    Abstract: Chip stack type semiconductor package and method for fabricating the same, the package including a lower chip having a center pad formation surface defined at a bottom thereof, an upper chip stacked on the lower chip by being adhered to a top surface of the lower chip having no center pad formed thereon and having a center pad formation surface defined at a top surface thereof, both surface adhesive insulating tapes attached on regions spaced from, and positioned left and right sides of respective center pads formed in the center pad formation surfaces of the lower chip and the upper chip, leads having inner lead portions inside of a molded body of an encapsulation resin and outer lead portions exposed outside of the molded body and both end portions of the leads attached to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the upper chip and to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the lower chip oppos
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: January 23, 2001
    Assignee: Hyundai Electronics Industries Co., LTD
    Inventors: Hee Joong Suh, Bog Kyou Lee