Patents by Inventor Heejune Lee

Heejune Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072782
    Abstract: A digital droop detector for detecting whether a droop occurs in a power supply voltage, may include processing circuitry configured to, detect a voltage level change of a power supply voltage in response to a clock signal, the detecting the voltage level change including converting the detected voltage level change into a first code, correct at least one nonlinearity included in the first code, the correcting including converting the first code into a second code and a target range, and adjust a delay magnitude of the clock signal based on the second code.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sangheon LEE, Heewook SHIN, Heejune LEE, Jungho LEE, Youngjae CHO, Michael CHOI
  • Patent number: 11867757
    Abstract: A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: January 9, 2024
    Inventors: Heejune Lee, Jinwoo Park, Younghyo Park, Eunhye Oh, Sungno Lee, Youngjae Cho, Michael Choi
  • Patent number: 11698410
    Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: July 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunhye Oh, Hyochul Shin, Jinwoo Park, Sungno Lee, Younghyo Park, Yongki Lee, Heejune Lee, Youngjae Cho, Michael Choi
  • Publication number: 20220206062
    Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.
    Type: Application
    Filed: September 10, 2021
    Publication date: June 30, 2022
    Inventors: Eunhye Oh, Hyochul Shin, Jinwoo Park, Sungno Lee, Younghyo Park, Yongki Lee, Heejune Lee, Youngjae Cho, Michael Choi
  • Publication number: 20220187366
    Abstract: A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally.
    Type: Application
    Filed: September 2, 2021
    Publication date: June 16, 2022
    Inventors: Heejune Lee, Jinwoo Park, Younghyo Park, Eunhye Oh, Sungno Lee, Youngjae Cho, Michael Choi