Abstract: Field-programmable gate array and method to implement an artificial neural network. A trained model of the neural network is processed, in which weights are defined in a floating-point format, to quantize each set of weights to a respective reduced-precision format in dependence on effect of quantization on accuracy of the model. For each set of weights, a partitioning scheme is defined for a set of block memories of the apparatus such that a plurality k of those weights can be stored in each addressable location of the set of memories, wherein k differs for different sets of weights. The apparatus can be programmed to implement the neural network such that weights in each set are persistently stored in a set of block memories partitioned according to the partitioning scheme for that set of weights.

Abstract: The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.

Abstract: A computing system comprising a central processing unit (CPU), a memory processor and a memory device comprising a data array and an index array. The computing system is configured to store data lines comprising data elements in the data array and to store index lines comprising a plurality of memory indices in the index array. The memory indices indicate memory positions of data elements in the data array with respect to a start address of the data array. There is further provided a related computer implemented method and a related computer program product.

Abstract: Field-programmable gate array and method to implement an artificial neural network. A trained model of the neural network is processed, in which weights are defined in a floating-point format, to quantize each set of weights to a respective reduced-precision format in dependence on effect of quantization on accuracy of the model. For each set of weights, a partitioning scheme is defined for a set of block memories of the apparatus such that a plurality k of those weights can be stored in each addressable location of the set of memories, wherein k differs for different sets of weights. The apparatus can be programmed to implement the neural network such that weights in each set are persistently stored in a set of block memories partitioned according to the partitioning scheme for that set of weights.

Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.

Abstract: The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.

Abstract: Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.

Abstract: Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.

Abstract: Embodiments of the present invention provide methods, computer program products, and systems for solving a linear equation system using a hardware-implemented extended solver, wherein a calculation precision is adapted in each iteration step of a solving process is provided. Embodiments of the present invention can be used to perform on-the-fly interpolations using the data associated with the highest resolution of the three-dimensional finite element voxel model to a lower resolution than the highest resolution as well as to perform solving computations of the solving process in the lower resolution.

Abstract: A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

Abstract: A computing system comprising a central processing unit (CPU), a memory processor and a memory device comprising a data array and an index array. The computing system is configured to store data lines comprising data elements in the data array and to store index lines comprising a plurality of memory indices in the index array. The memory indices indicate memory positions of data elements in the data array with respect to a start address of the data array. There is further provided a related computer implemented method and a related computer program product.

Abstract: A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

Abstract: An iterative refinement apparatus configured to generate data defining a solution vector x for a linear system represented by Ax=b, where A is a predetermined matrix and b is a predetermined vector. An outer solver processes input data, defining the matrix A and vector b, in accordance with an outer loop of an iterative refinement method to generate said data defining the solution vector x. An inner solver processes data items in accordance with an inner loop of the iterative refinement method. The inner solver is configured to process said data items having variable bit-width and data format. A precision controller determines the bit-widths and data formats of the data items adaptively in dependence on the results of the processing steps of the iterative refinement method; the precision controller configured to control operation of the inner solver for processing said data items with the bit-widths and data formats.

Abstract: Embodiments are directed to a heterogeneous system for dynamically mapping library calls to one of a plurality of processing platforms. The plurality of processing platforms include a central processing unit (CPU) and one or more acceleration units as co-processing units. The system includes an interposer configured to intercept the library calls from an application programming interface (API) and to map the library calls to one of the plurality of processing platforms according to a classification scheme based on an affinity table. The affinity table includes call signatures representing input parameters of sample library calls. Furthermore, the affinity table includes one or more performance parameters of the sample library calls for each of the processing platforms. The performance parameters indicate the performance of the sample library calls on the respective processing platform. Also included are a related method and a related computer program product.

Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.

Abstract: A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

Abstract: Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.

Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.

Abstract: Embodiments of the present invention provide methods, computer program products, and systems for solving a linear equation system using a hardware-implemented extended solver, wherein a calculation precision is adapted in each iteration step of a solving process is provided. Embodiments of the present invention can be used to perform on-the-fly interpolations using the data associated with the highest resolution of the three-dimensional finite element voxel model to a lower resolution than the highest resolution as well as to perform solving computations of the solving process in the lower resolution.

Abstract: Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.