Abstract: Conductions and vias between different, stacked metallic layers of a semiconductor device may be mechanically damaged by mechanical strain. According to an exemplary embodiment of the present invention, this mechanical strain may be transferred through the layer structure to the substrate by a grid of grounding structures and isolation and passivation layers which are connected by the grounding structures. This may provide for an enhancement of the lifetime of the semiconductor devices.

Abstract: The present invention relates to an electronic device whose component body contains at least one stress relief element (4), a substrate (1) with an upper surface and side walls at least one circuit element (2) located on said substrate (1) and at least one passivation and/or isolating layer (3) placed on said substrate (1), whereby said isolating layer (3) covers said at least one circuit element (2) and/or said substrate (1) and contains a top surface, at least one outer side surface which is located towards a side wall of said substrate and at least one outer edge, which is formed by said top surface and said at least one outer side surface, characterized in that at least one stress relief element (4) is made out of a ductile material and simultaneously a) covers the top surface of said passivation and/or isolating layer (3); and b) overlaps said outer edge of said passivation and/or isolating layer (3); and c) extends along said outer surface of said passivation and/or isolating layer (3); and d1) con

Abstract: Conductions and vias between different, stacked metallic layers of a semiconductor device may be mechanically damaged by mechanical strain. According to an exemplary embodiment of the present invention, this mechanical strain may be transferred through the layer structure to the substrate by a grid of grounding structures and isolation and passivation layers which are connected by the grounding structures. This may provide for an enhancement of the lifetime of the semiconductor devices.

Abstract: The invention relates to a method of manufacturing a polycrystalline semiconductor resistance layer of silicon on a silicon body. First an insulating layer is formed on the silicon body and then a polycrystalline silicon layer is deposited. To the deposited polycrystalline silicon layer is applied a further polycrystalline silicon layer having a crystallite structure coarser with respect to that of the first polycrystalline silicon layer. The two polycrystalline silicon layers are additionally doped.

Abstract: The invention relates to a method of manufacturing a polycrystalline semiconductor resistance layer of silicon on a silicon body. First an insulating layer is formed on the silicon body and then a polycrystalline silicon layer is deposited. To the deposited polycrystalline silicon layer is applied a further polycrystalline silicon layer having a crystallite structure coarser with respect to that of the first polycrystalline silicon layer. The two polycrystalline silicon layers are additionally doped. The invention further relates to a silicon pressure sensor having such a resistance layer.

Abstract: A temperature sensor in the form of a temperature-dependent semiconductor resistor operating according to the current-spreading principle includes a semiconductor body of one conductivity type of silicon, which is provided on its lower side with a conductive layer and is provided on its upper side with at least one contact zone of the one conductivity type. The upper side is coated with a silicon oxide layer or a silicon nitride layer. In order for the given resistance value to be maintained more accurately and the temperature coefficient to have only a small spread, the semiconductor body is provided at its surface adjacent the silicon oxide layer or silicon nitride layer with a surface zone of the opposite conductivity type. Thus, it is possible to limit to a minimum value or to completely compensate for the influence of charges at the silicon oxide layer or silicon nitride layer.