Abstract: A wide band constant duty cycle pulse train processing circuit where the pulse train frequency varies is proposed. The circuit serves primarily to obtain the basic clock in decoding signals encoded in the bi-phase mark code and includes a pulse-shaping or wave-shaping circuit, which receives the data signals and is followed by a low-pass filter; a differential amplifier circuit, one input of which is connected to the output of the low-pass filter and the other input of which is connected to a variable voltage source; and a current source, controlled by the differential amplifier circuit, at the input of the wave-shaping circuit determining the pulse length. The closed control loop between the output and the input of the wave-shaping circuit that determines the pulse length causes the duty cycle established at the variable voltage source to be maintained over wide ranges of the incident pulse train frequency.

Abstract: To obtain a switching signal whenever a fault occurs in the synchronization signals of a video signal, a fault detection circuit has a counter which receives the signals to be tested at its clock input and reference signals at its control input. The reference signals have the same pulse frequency as the signals to be tested and are obtained from the signals to be tested by a change in keying ratio. The output of the counter is connected in its "clear" input and also, via a monostable flip-flop, to an input from an OR-gate. The other input of the OR-gate receives the reference signals via a diode and an RC-link. The desired switching signal is obtained at the output of the OR-gate.

Abstract: A first self-timing signal bi-phase-mark coded and having a data portion and a synchronization portion is to be sequenced by a second signal also having a data and a synchronization portion. The signals derived by differentiating only the level change at the end of each bit cell phase-lock an oscillator whose output provides the basic timing for a modulator stage. In the modulator stage, a flip-flop first changes state under control of the first signal. At the start of the synchronization portion of the first signal, a comparator furnishes a signal which switches control of the flip-flop to signals derived from differentiation of the second signal. When the second signal is binary coded, a NAND gate modulates the pulses from the second signal by pulses resulting from differentiating negative going edges of the signal derived from the phase-locked oscillator to create a signal for controlling the flip-flop so that it changes state in accordance with a bi-phase-mark code.

Abstract: Method of controlling with heightened accuracy a processing machine driven t different operating speeds and having a machine part moving through a predetermined full range, the processing machine, at an initial setting of the moving machine part, within a given tolerance range, repeatedly permitting start-up of a processing cycle that has been instituted in advance through a precontrolled time period dependent upon the operating speed and which includes a control commencement build-up time period and a full range displacement time period, which includes interposing a blocking time period between the control commencement build-up time period and the full range displacement time period, the blocking time period always ending at the same position in the displacement range of the moving machine part, blocking the full range displacement by the moving machine part until the end of the blocking time period, and advancing the start of the control commencement build-up time period in accordance with the blocking time

Abstract: Method of controlling with heightened accuracy a processing machine driven t different operating speeds and having a machine part moving through a predetermined full range, the processing machine, at an initial setting of the moving machine part, within a given tolerance range, repeatedly permitting start-up of a processing cycle that has been instituted in advance through a precontrolled time period dependent upon the operating speed and which includes a control commencement build-up time period and a full range displacement time period, which includes interposing a blocking time period between the control commencement build-up time period and the full range displacement time period, the blocking time period always ending at the same position in the displacement range of the moving machine part, blocking the full range displacement by the moving machine part until the end of the blocking time period, and advancing the start of the control commencement build-up time period in accordance with the blocking time