Abstract: A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor.

Abstract: Improved micro fuel cells suitable for portable electrical devices are provided, and processes for forming such cells. In one embodiment of the invention, silicon substrates are used both as the gas delivery structure for the fuel and the oxidant, and as the current collectors. Such use of silicon is advantageous in that it becomes possible both to utilize micromachining and lithographic techniques to form the desired structures, e.g., the gas delivery channels, and also to integrate the fuel cell with silicon-based control circuitry. Advantageously, the silicon substrates comprise both gas delivery tunnels and porous silicon gas diffusion regions formed over the tunnels in the surface of the substrate, i.e., the porous regions over the gas delivery tunnels are integral with the silicon substrate. In another embodiment of the invention, a monolithic structure is employed.

Abstract: A process for fabricating a multi-layer interconnect in which an organic low-k material is formed over a topographic substrate. An insulator such as silicon dioxide is formed over the organic low-k material. The insulator is planarized. Contact holes or vias are then etched in the two-layer stack.

Abstract: The specification describes an interferometric in-situ end point detection technique for plasma etching in which the end point is predicted before any overetching occurs. It is based on the recognition that the wavelength of the monitoring beam can be selected so that only a single interferometric fringe appears before clearing. Knowing there is only one fringe, detection is simplified and the etching process can be terminated while a finite but small thickness of the layer remains. This allows etching partial thicknesses of layers. It also allows a two step etch process wherein the etch chemistry can be changed to a highly selective etch to complete clearing of the layer.

Abstract: A process for device fabrication in which polarized light is used to monitor film thickness. The polarized light is made incident on the surface of a substrate with a film thereon that has a different reflectivity than that of the underlying substrate. The surface of the film is non-planar, either by virtue of the fact that the film is formed over a substrate with a non-planar surface, or because there is a patterned layer formed over the film, or both. The substrate is subjected to conditions that change the thickness of the film on the substrate. The polarized light that is reflected from the substrate is detected at a selected wavelength or wavelengths and a trace of the intensity of the reflected light both parallel and perpendicular to the substrate surface over time is obtained. This trace is compared to a model trace which is obtained by approximating the film thickness, and the relative amount of the areas of different reflectivity on the substrate surface.

Abstract: The present invention is predicated upon the fact that a process signature from a plasma process used in fabricating integrated circuits contains information about phenomena which cause variations in the fabrication process such as age of the plasma reactor, densities of the wafers exposed to the plasma, chemistry of the plasma, and concentration of the remaining material. In accordance with the present invention, a method for using neural networks to determine plasma etch end-point times in an integrated circuit fabrication process is disclosed. The end-point time is based on in-situ monitoring of at least two parameters during the plasma etch process. After the neural network is trained to associate a certain condition or set of conditions with the endpoint of the process, the neural network is used to control the process.