Abstract: A method for forming an adhesion layer in contact with a first surface of a substrate and a surface of a layer having electrically conductive properties using electrophotographic imaging compound as a mask is provided. The adhesion layer improves the lamination properties of the electrically conductive layer to the substrate. The improved lamination properties to facilitate and increase the reliability and quality of a resulting product having an electronic circuit formed in accordance with the present invention. The method disclosed herein is well suited for use with rigid polymeric substrates and flexible polymeric substrates.

Abstract: The present invention provides a method for forming an adhesion layer in contact with a first surface of a substrate and a surface of a layer having electrically conductive properties using electrophotographic imaging compound as a mask. The adhesion layer improves the lamination properties of the electrically conductive layer to the substrate. The improved lamination properties to facilitate and increase the reliability and quality of a resulting product having an electronic circuit formed in accordance with the present invention. The method disclosed herein is well suited for use with rigid polymeric substrates and flexible polymeric substrates.

Abstract: The present invention provides a method for forming an adhesion layer in contact with a first surface of a substrate and a surface of a layer having electrically conductive properties using electrophotographic imaging compound as a mask. The adhesion layer improves the lamination properties of the electrically conductive layer to the substrate. The improved lamination properties to facilitate and increase the reliability and quality of a resulting product having an electronic circuit formed in accordance with the present invention. The method disclosed herein is well suited for use with rigid polymeric substrates and flexible polymeric substrates.

Abstract: A thin film transistor array fabricated on a polyimide substrate forms a backplane for an electronic display. The thin film transistor array incorporates gate electrodes, a gate insulating layer, semiconducting channel layers deposited on top of the gate insulating layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer. An insulating encapsulation layer is positioned on the channel layer. The layers are deposited onto the polyimide substrate using PECVD and etched using photolithography to form the backplane.

Abstract: A thin film transistor array fabricated on a polyimide substrate forms a backplane for an electronic display. The thin film transistor array incorporates gate electrodes, a gate insulating layer, semiconducting channel layers deposited on top of the gate insulating layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer. An insulating encapsulation layer is positioned on the channel layer. The layers are deposited onto the polyimide substrate using PECVD and etched using photolithography to form the backplane.

Abstract: A thin film transistor array fabricated on a polyimide substrate forms a backplane for an electronic display. The thin film transistor array incorporates gate electrodes, a gate insulating layer, semiconducting channel layers deposited on top of the gate insulating layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer. An insulating encapsulation layer is positioned on the channel layer. The layers are deposited onto the polyimide substrate using PECVD and etched using photolithography to form the backplane.

Abstract: A thin film transistor array fabricated on a polyimide substrate forms a backplane for an electronic display. The thin film transistor array incorporates gate electrodes, a gate insulating layer, semiconducting channel layers deposited on top of the gate insulating layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer. An insulating encapsulation layer is positioned on the channel layer. The layers are deposited onto the polyimide substrate using PECVD and etched using photolithography to form the backplane.

Abstract: A process sequence is disclosed for fabricating arrays of Thin Film Transistors by printing metallic conductors for the gate and data lines and possibly the Indium Tin Oxide Pixel electrode as well. The process eliminates conventional step-and-repeat photolithographic patterning, and provides high conductivity metallization for large arrays. These arrays may be used in displays, detectors and scanners.

Abstract: Amorphous silicon thin-film transistors on glass foil are made using exclusively electrophotographic printing for pattern formation, contact hole opening, and device isolation. Toner etch masks are applied by feeding the glass substrate through a laser printer or photocopier, or from laser-printed patterns on transfer paper. This all-printed patterning is a low-cost, large-area circuit processing technology, suitable for producing backplanes for active matrix liquid crystal displays.