Patents by Inventor Helmut Gottfried KATZGRABER

Helmut Gottfried KATZGRABER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11922337
    Abstract: A computing device, including memory, an accelerator device, and a processor. The processor may generate a plurality of data packs that each indicate an update to a variable of one or more variables of a combinatorial cost function. The processor may transmit the plurality of data packs to the accelerator device. The accelerator device may, for each data pack, retrieve a variable value of the variable indicated by the data pack and generate an updated variable value. The accelerator device may generate an updated cost function value based on the updated variable value. The accelerator device may be further configured to determine a transition probability using a Monte Carlo algorithm and may store the updated variable value and the updated cost function value with the transition probability. The accelerator device may output a final updated cost function value to the processor.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: March 5, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Matthias Troyer, Helmut Gottfried Katzgraber, Christopher Anand Pattison
  • Publication number: 20230359912
    Abstract: A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
  • Patent number: 11755941
    Abstract: A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: September 12, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Poulami Das, Nicolas Guillaume Delfosse, Christopher Anand Pattison, Srilatha Manne, Douglas Carmean, Krysta Marie Svore, Helmut Gottfried Katzgraber
  • Patent number: 11720071
    Abstract: A computing device is provided, including memory storing a cost function of a plurality of variables. The computing device may further include a processor configured to, for a stochastic simulation algorithm, compute a control parameter upper bound. The processor may compute a control parameter lower bound. The processor may compute a plurality of intermediate control parameter values within a control parameter range between the control parameter lower bound and the control parameter upper bound. The processor may compute an estimated minimum or an estimated maximum of the cost function using the stochastic simulation algorithm with the control parameter upper bound, the control parameter lower bound, and the plurality of intermediate control parameter values. A plurality of copies of the cost function may be simulated with a respective plurality of seed values.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: August 8, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Damian Silvio Steiger, Helmut Gottfried Katzgraber, Matthias Troyer, Christopher Anand Pattison
  • Publication number: 20230153665
    Abstract: A computing device, including memory, an accelerator device, and a processor. The processor may generate a plurality of data packs that each indicate an update to a variable of one or more variables of a combinatorial cost function. The processor may transmit the plurality of data packs to the accelerator device. The accelerator device may, for each data pack, retrieve a variable value of the variable indicated by the data pack and generate an updated variable value. The accelerator device may generate an updated cost function value based on the updated variable value. The accelerator device may be further configured to determine a transition probability using a Monte Carlo algorithm and may store the updated variable value and the updated cost function value with the transition probability. The accelerator device may output a final updated cost function value to the processor.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 18, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Matthias TROYER, Helmut Gottfried KATZGRABER, Christopher Anand PATTISON
  • Patent number: 11630703
    Abstract: A computing device is provided, including a cluster update accelerator circuit configured to receive signals encoding a combinatorial cost function of a plurality of variables and a connectivity graph for the combinatorial cost function. In an energy sum phase, the cluster update accelerator circuit may determine a respective plurality of accumulated energy change values for the combinatorial cost function based at least in part on the connectivity graph. In an update phase, the cluster update accelerator circuit may determine a respective update indicator bit for each accumulated energy change value. In an encoder phase, based on the plurality of update indicator bits, the cluster update accelerator circuit may select a largest update-indicated cluster of the variables included in the connectivity graph. The cluster update accelerator circuit may output an instruction to update the variables included in the largest update-indicated cluster.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 18, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Christopher Anand Pattison, Helmut Gottfried Katzgraber, Matthias Troyer
  • Patent number: 11579947
    Abstract: A method for use with a computing device. The method may include receiving a data set including a plurality of univariate data points and determining a target kernel bandwidth for a kernel density estimator (KDE). Determining the target kernel bandwidth may include computing a plurality of sample KDEs and selecting the target kernel bandwidth based on the sample KDEs. The method may further include computing the KDE for the data set using the target kernel bandwidth. For one or more tail regions of the data set, the method may further include computing one or more respective tail extensions. The method may further include computing and outputting a renormalized piecewise density estimator that, in each tail region, equals a renormalization of the respective tail extension for that tail region, and, outside the one or more tail regions, equals a renormalization of the KDE.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 14, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Firas Hamze, Helmut Gottfried Katzgraber
  • Patent number: 11562273
    Abstract: A computing device, including memory, an accelerator device, and a processor. The processor may generate a plurality of data packs that each indicate an update to a variable of one or more variables of a combinatorial cost function. The processor may transmit the plurality of data packs to the accelerator device. The accelerator device may, for each data pack, retrieve a variable value of the variable indicated by the data pack and generate an updated variable value. The accelerator device may generate an updated cost function value based on the updated variable value. The accelerator device may be further configured to determine a transition probability using a Monte Carlo algorithm and may store the updated variable value and the updated cost function value with the transition probability. The accelerator device may output a final updated cost function value to the processor.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: January 24, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Matthias Troyer, Helmut Gottfried Katzgraber, Christopher Anand Pattison
  • Publication number: 20220382225
    Abstract: A computing device is provided, including memory storing a cost function of a plurality of variables. The computing device may further include a processor configured to, for a stochastic simulation algorithm, compute a control parameter upper bound. The processor may compute a control parameter lower bound. The processor may compute a plurality of intermediate control parameter values within a control parameter range between the control parameter lower bound and the control parameter upper bound. The processor may compute an estimated minimum or an estimated maximum of the cost function using the stochastic simulation algorithm with the control parameter upper bound, the control parameter lower bound, and the plurality of intermediate control parameter values. A plurality of copies of the cost function may be simulated with a respective plurality of seed values.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 1, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Damian Silvio STEIGER, Helmut Gottfried KATZGRABER, Matthias TROYER, Christopher Anand PATTISON
  • Publication number: 20220385306
    Abstract: A quantum computing device comprises a surface code lattice that includes/logical qubits, where/is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the/logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
  • Patent number: 11410070
    Abstract: A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 9, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Poulami Das, Nicolas Guillaume Delfosse, Christopher Anand Pattison, Srilatha Manne, Douglas Carmean, Krysta Marie Svore, Helmut Gottfried Katzgraber
  • Patent number: 11402809
    Abstract: A computing device is provided, including memory storing a cost function of a plurality of variables. The computing device may further include a processor configured to, for a stochastic simulation algorithm, compute a control parameter upper bound. The processor may compute a control parameter lower bound. The processor may compute a plurality of intermediate control parameter values within a control parameter range between the control parameter lower bound and the control parameter upper bound. The processor may compute an estimated minimum or an estimated maximum of the cost function using the stochastic simulation algorithm with the control parameter upper bound, the control parameter lower bound, and the plurality of intermediate control parameter values. A plurality of copies of the cost function may be simulated with a respective plurality of seed values.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Damian Silvio Steiger, Helmut Gottfried Katzgraber, Matthias Troyer, Christopher Anand Pattison
  • Publication number: 20220067245
    Abstract: In a method to digitally simulate an evolving quantum state of a qubit register of a quantum computer, the quantum state is represented as a state vector of complex-valued amplitudes, where each amplitude is associated with an individual qubit of the qubit register. A directed acyclic graph defining a set of quantum gates of a quantum-computer program is then received. A linear order for the DAG is constructed by minimizing a partial cost function successively re-computed during construction of the linear order, the partial cost function approximating a cost of transforming the state vector according to a subset of the set of quantum gates applied in the linear order. The state vector is transformed according to the set of quantum gates applied in the linear order, and one or more of the complex-valued amplitudes of the transformed state vector are computationally output.
    Type: Application
    Filed: October 14, 2020
    Publication date: March 3, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Damian Silvio STEIGER, Thomas HAENER, Martin Henri ROETTELER, Helmut Gottfried KATZGRABER
  • Publication number: 20220050731
    Abstract: A method for use with a computing device. The method may include receiving a data set including a plurality of univariate data points and determining a target kernel bandwidth for a kernel density estimator (KDE). Determining the target kernel bandwidth may include computing a plurality of sample KDEs and selecting the target kernel bandwidth based on the sample KDEs. The method may further include computing the KDE for the data set using the target kernel bandwidth. For one or more tail regions of the data set, the method may further include computing one or more respective tail extensions. The method may further include computing and outputting a renormalized piecewise density estimator that, in each tail region, equals a renormalization of the respective tail extension for that tail region, and, outside the one or more tail regions, equals a renormalization of the KDE.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 17, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Firas HAMZE, Helmut Gottfried KATZGRABER
  • Publication number: 20210216374
    Abstract: A computing device is provided, including a cluster update accelerator circuit configured to receive signals encoding a combinatorial cost function of a plurality of variables and a connectivity graph for the combinatorial cost function. In an energy sum phase, the cluster update accelerator circuit may determine a respective plurality of accumulated energy change values for the combinatorial cost function based at least in part on the connectivity graph. In an update phase, the cluster update accelerator circuit may determine a respective update indicator bit for each accumulated energy change value. In an encoder phase, based on the plurality of update indicator bits, the cluster update accelerator circuit may select a largest update-indicated cluster of the variables included in the connectivity graph. The cluster update accelerator circuit may output an instruction to update the variables included in the largest update-indicated cluster.
    Type: Application
    Filed: January 15, 2020
    Publication date: July 15, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Christopher Anand PATTISON, Helmut Gottfried KATZGRABER, Matthias TROYER
  • Publication number: 20210096520
    Abstract: A computing device is provided, including memory storing a cost function of a plurality of variables. The computing device may further include a processor configured to, for a stochastic simulation algorithm, compute a control parameter upper bound. The processor may compute a control parameter lower bound. The processor may compute a plurality of intermediate control parameter values within a control parameter range between the control parameter lower bound and the control parameter upper bound. The processor may compute an estimated minimum or an estimated maximum of the cost function using the stochastic simulation algorithm with the control parameter upper bound, the control parameter lower bound, and the plurality of intermediate control parameter values. A plurality of copies of the cost function may be simulated with a respective plurality of seed values.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 1, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Damian Silvio STEIGER, Helmut Gottfried KATZGRABER, Matthias TROYER, Christopher Anand PATTISON
  • Publication number: 20210042652
    Abstract: A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.
    Type: Application
    Filed: November 18, 2019
    Publication date: February 11, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
  • Publication number: 20210042651
    Abstract: A quantum computing device comprises at least one quantum register including l logical qubits, where l is a positive integer. The quantum computing device further includes a set of d decoder blocks coupled to the at least one quantum register, where d<2*l. In this way, the decoder blocks may share decoding requests generated by the logical qubits.
    Type: Application
    Filed: November 18, 2019
    Publication date: February 11, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
  • Publication number: 20210042650
    Abstract: A quantum computing device comprises at least one quantum register including a plurality of qubits, and a hardware decoder. The hardware decoder is configured to: receive syndrome data from one or more of the plurality of qubits; and decode the received syndrome data by implementing a Union-Find decoding algorithm via a hardware microarchitecture including two or more pipeline stages.
    Type: Application
    Filed: November 15, 2019
    Publication date: February 11, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
  • Publication number: 20200257998
    Abstract: A computing device, including memory, an accelerator device, and a processor. The processor may generate a plurality of data packs that each indicate an update to a variable of one or more variables of a combinatorial cost function. The processor may transmit the plurality of data packs to the accelerator device. The accelerator device may, for each data pack, retrieve a variable value of the variable indicated by the data pack and generate an updated variable value. The accelerator device may generate an updated cost function value based on the updated variable value. The accelerator device may be further configured to determine a transition probability using a Monte Carlo algorithm and may store the updated variable value and the updated cost function value with the transition probability. The accelerator device may output a final updated cost function value to the processor.
    Type: Application
    Filed: February 11, 2019
    Publication date: August 13, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Matthias TROYER, Helmut Gottfried KATZGRABER, Christopher Anand PATTISON