Patents by Inventor Hemanshu D. Bhatt
Hemanshu D. Bhatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9739934Abstract: The present technology provides an illustrative method for preparing fibers with desirable optical characteristics. The method includes providing a fiber that comprises a core layer and a cladding layer located around the core layer. The method further includes applying a nanostructure template to the cladding layer to form one or more photonic nanostructures having nanostructure scales and compressing the core layer to cause the core layer to bulge and form air gaps between the core layer and the one or more photonic nanostructures.Type: GrantFiled: January 6, 2015Date of Patent: August 22, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventors: Hemanshu D. Bhatt, Sunit D. Tyagi
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Publication number: 20150147559Abstract: The present technology provides an illustrative method for preparing fibers with desirable optical characteristics. The method includes providing a fiber that comprises a core layer and a cladding layer located around the core layer. The method further includes applying a nanostructure template to the cladding layer to form one or more photonic nanostructures having nanostructure scales and compressing the core layer to cause the core layer to bulge and form air gaps between the core layer and the one or more photonic nanostructures.Type: ApplicationFiled: January 6, 2015Publication date: May 28, 2015Inventors: Hemanshu D. BHATT, Sunit D. TYAGI
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Patent number: 8940199Abstract: The present technology provides an illustrative method for preparing fibers with desirable optical characteristics. The method includes providing a fiber that comprises a core layer and a cladding layer located around the core layer. The method further includes applying a nanostructure template to the cladding layer to form one or more photonic nanostructures having nanostructure scales and compressing the core layer to cause the core layer to bulge and form air gaps between the core layer and the one or more photonic nanostructures.Type: GrantFiled: October 17, 2011Date of Patent: January 27, 2015Assignee: Empire Technology Development LLCInventors: Hemanshu D. Bhatt, Sunit D. Tyagi
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Patent number: 8772865Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.Type: GrantFiled: September 26, 2012Date of Patent: July 8, 2014Assignee: Semiconductor Components Industries, LLCInventors: Jeffrey Pearse, Prasad Venkatraman, James Sellers, Hemanshu D. Bhatt
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Publication number: 20140147652Abstract: The present technology provides an illustrative method for preparing fibers with desirable optical characteristics. The method includes providing a fiber that comprises a core layer and a cladding layer located around the core layer. The method further includes applying a nanostructure template to the cladding layer to form one or more photonic nanostructures having nanostructure scales and compressing the core layer to cause the core layer to bulge and form air gaps between the core layer and the one or more photonic nanostructures.Type: ApplicationFiled: October 17, 2011Publication date: May 29, 2014Inventors: Hemanshu D. Bhatt, Sunit D. Tyagi
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Publication number: 20140084363Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.Type: ApplicationFiled: September 26, 2012Publication date: March 27, 2014Inventors: Jeffrey Pearse, Prasad Venkatraman, James Sellers, Hemanshu D. Bhatt
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Patent number: 8304314Abstract: In one embodiment, a method of forming an MOS transistor includes forming the MOS transistor to have an active region and a termination region. Within the termination region the method includes forming a plurality of trenches having a conductor within the plurality of trenches. The method also includes forming another conductor to make electrical contact to one of the conductors within the plurality of trenches.Type: GrantFiled: September 24, 2008Date of Patent: November 6, 2012Assignee: Semiconductor Components Industries, LLCInventors: Jeffrey Pearse, Prasad Venkatraman, James Sellers, Hemanshu D. Bhatt
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Patent number: 7915122Abstract: A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer.Type: GrantFiled: December 20, 2005Date of Patent: March 29, 2011Assignee: Nantero, Inc.Inventors: Richard J. Carter, Hemanshu D. Bhatt, Shiqun Gu, Peter A. Burke, James R. B. Elmer, Sey-Shing Sun, Byung-Sung Kwak, Verne Hornback
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Publication number: 20100072544Abstract: In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.Type: ApplicationFiled: September 24, 2008Publication date: March 25, 2010Inventors: Jeffrey Pearse, Prasad Venkatraman, James Sellers, Hemanshu D. Bhatt
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Patent number: 7582566Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.Type: GrantFiled: January 24, 2008Date of Patent: September 1, 2009Assignee: LSI Logic CorporationInventors: Derryl D. J. Allman, Hemanshu D. Bhatt, Charles E. May, Peter Austin Burke, Byung-Sung Kwak, Sey-Shing Sun, David T. Price, David Pritchard
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Patent number: 7456076Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.Type: GrantFiled: August 18, 2006Date of Patent: November 25, 2008Assignee: LSI CorporationInventors: Santosh S. Menon, Hemanshu D. Bhatt
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Patent number: 7436040Abstract: A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.Type: GrantFiled: December 29, 2005Date of Patent: October 14, 2008Assignee: LSI CorporationInventors: Derryl D. J. Allman, Hemanshu D. Bhatt, Charles E. May, Peter Austin Burke, Byung-Sung Kwak, Sey-Shing Sun, David T. Price, David Pritchard
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Patent number: 7402770Abstract: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.Type: GrantFiled: November 9, 2005Date of Patent: July 22, 2008Assignee: LSI Logic CorporationInventors: Sey-Shing Sun, Hemanshu D. Bhatt, Peter A. Burke, Richard J. Carter
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Patent number: 7384801Abstract: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.Type: GrantFiled: June 11, 2007Date of Patent: June 10, 2008Assignee: LSI CorporationInventors: Hemanshu D. Bhatt, Jan Fure, Derryl D. J. Allman
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Publication number: 20080132065Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.Type: ApplicationFiled: January 24, 2008Publication date: June 5, 2008Inventors: Derryl D. J. Allman, Hemanshu D. Bhatt, Charles E. May, Peter Austin Burke, Byung-Sung Kwak, Sey-Shing Sun, David T. Price, David Pritchard
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Patent number: 7361965Abstract: A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.Type: GrantFiled: December 29, 2005Date of Patent: April 22, 2008Inventors: Derryl D. J. Allman, Hemanshu D. Bhatt, Charles E. May, Peter Austin Burke, Byung-Sung Kwak, Sey-Shing Sun, David T. Price, David Pritchard
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Patent number: 7259083Abstract: The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.Type: GrantFiled: October 22, 2004Date of Patent: August 21, 2007Assignee: LSI CorporationInventors: Santosh S. Menon, Hemanshu D. Bhatt, David Pritchard
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Patent number: 7253497Abstract: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.Type: GrantFiled: July 2, 2003Date of Patent: August 7, 2007Assignee: LSI CorporationInventors: Hemanshu D. Bhatt, Jan Fure, Derryl D. J. Allman
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Patent number: 7122436Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.Type: GrantFiled: September 16, 2004Date of Patent: October 17, 2006Assignee: LSI Logic CorporationInventors: Santosh S. Menon, Hemanshu D. Bhatt
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Patent number: 6967177Abstract: An apparatus for controlling the substrate temperature of a substrate during processing of the substrate at a process energy. A chuck temperature input receives temperature measurements from temperature sensors at a substrate chuck, and a temperature set point input receives temperature set points. The temperature set points define a range of temperatures within which the apparatus maintains the substrate temperature. A chuck temperature controller output sends control signals to a chuck temperature controller, which signals are operable to selectively increase and decrease the chuck temperature. A process energy output sends control signals that are operable to selectively increase and decrease the process energy during the processing of the substrate. A controller compares the temperature measurements received from the temperature sensors at the substrate chuck through the chuck temperature input to the temperature set points received through the temperature set point input.Type: GrantFiled: September 27, 2000Date of Patent: November 22, 2005Assignee: LSI Logic CorporationInventors: Charles E. May, Hemanshu D. Bhatt