Abstract: The invention conveys network related information utilizing a single bit within a data cell. This is facilitated through a statistical analysis of a plurality of such single bits collected over a period of time from multiple data cells, and provides a level of intelligence beyond a simple indication of whether or not a particular parameter has exceeded a preset threshold. Thus a switch compiling such information can convey more accurate statistical information with respect to a varying parameter related to data cells (such as queue size, current transmission rate or link utilization) being sent to the various receivers within the network. Each receiver can then apply a suitable filter to the stream of received bits to extract the appropriate information, and send that information back to the source. In response, the source adapts the transmission rate or amount of data cells being sent to the switch accordingly.

Abstract: A packet switch of the type in which packets received in the switch are stored in memory until they are output. In the switch fabric of the switch, packets are serially received in input shift registers wide enough to store an entire packet, output in parallel to memory which is as wide as the input shift register, moved in parallel in the memory, and output in parallel to an output shift register. The bus connecting the input shift registers, the output shift register, and the memory is as wide as the input shift register, but does not cross the boundaries of the semiconductor chips making up the switch fabric, thus avoiding the electrical problems of very wide buses. In the disclosed implementation, there are 14 input lines and 14 output lines. A switch memory is associated with each output line and receives packets from all 14 input lines, accepting only those destined for the output line associated with the input line.