Abstract: The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further con

Abstract: A computer-implemented method for simulation of an integrated circuit for yield analysis includes: a) for plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of circuits; b) selecting at least one sample from each initial set randomly and combining into initial simulation set; c) running initial simulation of operation of circuit, applying initial simulation set, the operation having passing/failing criterion; d) if fails: storing samples of initial set into initial sampling distributions for each variable; e) repeating steps b)-d) until sufficient failures obtained; f) building importance sampling distribution based on each initial sampling distribution, the importance distribution having lower, center, upper portions; g) generating secondary simulation set by drawing samples from importance sampling distribution for each variable; h) simulating circuit by applying the secondary set; i) repeating steps g)-h); j) mapping resulting yie

Abstract: The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further con

Abstract: The present disclosure relates to a computer-implemented method for simulation of an integrated circuit for yield analysis of the integrated circuit, the method comprising the steps of: a) for a plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of the integrated circuits; b) selecting at least one sample from each initial sampling set randomly and combining the selected samples into an initial simulation set; c) running an initial simulation of an operation of the integrated circuit, applying the initial simulation set, wherein the operation has a criterion for passing and failing the operation; d) if the initial simulation fails: storing the samples of the initial simulation set into initial sampling distributions for each variable; e) repeating steps b)-d) until a sufficient number of failures have been obtained; f) building an importance sampling distribution based on each initial sampling distribution, the importance sampling di

Abstract: The present disclosure relates to a computer-implemented method for implementing an integrated circuit comprising at least one random-access memory, the method comprising the steps of: defining a plurality of memory portions of the random-access memory and obtaining sizes of the memory portions; for each memory portion, generating a memory cell array block, the memory cell array blocks corresponding to the sizes of the memory portions, wherein instances of the memory cell array blocks are inferred into a description of the integrated circuit in a hardware description language; for each memory cell array block, generating timing models and physical models; synthesizing the description of the integrated circuit in the hardware description language, including peripheral logic for the memory cell array blocks, to a schematic representation of circuit elements; placing the circuit elements, including the memory cell array blocks and the peripheral logic, on the integrated circuit and routing wires between the circ