Abstract: An FM receiver having an RF section, a first tunable mixer stage for the frequency conversion of a desired RF FM reception signal into a first intermediate frequency signal, an IF device and an FM demodulator. In order to enhance the integration of the apparatus, while maintaining a signal processing ability which is free from distortion, the FM receiver includes circuitry incorporated in the signal path for converting a single-phase signal into a pair of signals in mutual phase quadrature. The pair of phase-quadrature signals is applied to in-phase and quadrature signal paths of the IF device. The IF device having a polyphase IF filter incorporated in the in-phase and quadrature signal paths and has a bandpass characteristic which is symmetrical around its resonance frequency. The polyphase IF filter is coupled to the FM demodulator.

Abstract: An FM receiver includes an RF section, a first mixer stage for converting a desired RF reception signal into a first IF signal having a carrier frequency located on average at a first intermediate frequency, a first IF section for selecting the first IF signal, and a second mixer stage for converting the first IF signal into a second IF signal having a carrier frequency located on average at a second intermediate frequency. The second intermediate frequency is below the first intermediate frequency. A second IF section selects the second IF signal and is coupled to an FM demodulator for demodulating the baseband modulation signal of the desired RF reception signal, followed by a low-pass filter for selecting the baseband modulation signal.

Abstract: An adjustable resistance device having a first parallel arrangement (1) of a first resistor and a first positive-feedback transconductor is provided with a control circuit (20) for controlling the controllable resistance section in the first parallel arrangement (1), which control circuit (20) includes a control loop including a second parallel arrangement (2) which is a copy of the first parallel arrangement (1). The control circuit (20) controls the controllable section of the second parallel arrangement (2) in such a manner that the negative resistance value formed by a second transconductor is substantially equal in magnitude to the resistance value of a second resistor, so that the second parallel arrangement (2) is bistable in the transition range.