Patents by Inventor Heng-Kuang Lin
Heng-Kuang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10847643Abstract: Provided is an enhancement mode HEMT device including a substrate, a channel layer, a barrier layer, a P-type semiconductor layer, a carrier providing layer, a gate electrode, a source electrode and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The P-type semiconductor layer is disposed on the barrier layer. The carrier providing layer is disposed on the sidewall of the P-type semiconductor layer and extends laterally away from the P-type semiconductor layer. The gate electrode is disposed on the P-type semiconductor layer. The source electrode and the drain electrode are disposed on the carrier providing layer and at two sides of the gate electrode. A method of forming an enhancement mode HEMT device is further provided.Type: GrantFiled: November 6, 2018Date of Patent: November 24, 2020Assignee: Nuvoton Technology CorporationInventors: Kuei-Yi Chu, Heng-Kuang Lin
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Patent number: 10446472Abstract: Provided is a nitride semiconductor device including a substrate, a nucleation layer, a buffer layer, a channel layer, a first electrode, and a second electrode. The substrate has a first surface and a second surface opposite to the first surface. The nucleation layer, the buffer layer, the channel layer, and the barrier layer are sequentially disposed on the first surface of the substrate. The first electrode layer and the second electrode layer are disposed on the barrier layer. A first void penetrates through the substrate, the nucleation layer, the buffer layer, the channel layer, and the barrier layer and exposes a portion of the first electrode.Type: GrantFiled: July 19, 2018Date of Patent: October 15, 2019Assignee: Nuvoton Technology CorporationInventors: Kuei-Yi Chu, Heng-Kuang Lin
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Patent number: 10431454Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a base, a buffer layer, a mask layer and a first GaN layer. The buffer layer is disposed on the base, wherein doped regions are disposed in a portion of the surface of the buffer layer. The mask layer is disposed on the buffer layer and located on the doped regions. The first GaN layer is disposed on the buffer layer and covers the mask layer.Type: GrantFiled: August 7, 2018Date of Patent: October 1, 2019Assignee: Nuvoton Technology CorporationInventors: Fang-Chang Hsueh, Heng-Kuang Lin
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Patent number: 10411098Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first stacked structure, a second stacked structure, an isolation layer and a gate. The first stacked structure is disposed on a substrate, and includes a first GaN channel layer disposed on the substrate and having an N crystal phase and a first barrier layer disposed on the first GaN channel layer. The second stacked structure is disposed on the substrate, and includes a second GaN channel layer disposed on the substrate and having a Ga crystal phase and a second barrier layer disposed on the second GaN channel layer. The isolation layer is disposed between the first stacked structure and the second stacked structure. The gate is disposed on the first stacked structure, the isolation layer and the second stacked structure.Type: GrantFiled: May 28, 2018Date of Patent: September 10, 2019Assignee: Nuvoton Technology CorporationInventors: Chih-Wei Chen, Heng-Kuang Lin
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Patent number: 10367088Abstract: A nitride semiconductor device is provided, including a substrate having a first surface and a second surface opposite to each other; a nucleation layer disposed on the first surface of the substrate; a doped nitride semiconductor layer disposed on the nucleation layer; a doped first buffer layer disposed on the doped nitride semiconductor layer; a channel layer disposed on the doped first buffer layer; a barrier layer disposed on the channel layer; a first electrode disposed on the barrier layer; a second electrode electrically connected to the doped nitride semiconductor layer; and a doped region disposed at least in a portion of the doped nitride semiconductor layer, wherein the doped region is extended from below the first electrode to be partially overlapped with the second electrode.Type: GrantFiled: November 12, 2018Date of Patent: July 30, 2019Assignee: Nuvoton Technology CorporationInventors: Kuei-Yi Chu, Heng-Kuang Lin, Jung-Tse Tsai, Shih-Po Lin, Chih-Wei Chen
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Publication number: 20190207019Abstract: Provided is an enhancement mode HEMT device including a substrate, a channel layer, a first barrier layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The first barrier layer is disposed on the channel layer. At least one trench penetrates through the first barrier layer and extends into the channel layer. The gate is disposed on the first barrier layer, fills in the at least one trench and is in contact with the channel layer. The source and the drain are disposed in the first barrier layer and the channel layer and located at two sides of the gate.Type: ApplicationFiled: November 15, 2018Publication date: July 4, 2019Applicant: Nuvoton Technology CorporationInventors: Jung-Tse Tsai, Heng-Kuang Lin
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Publication number: 20190207021Abstract: Provided is an enhancement mode HEMT device including a substrate, a channel layer, a barrier layer, a P-type semiconductor layer, a carrier providing layer, a gate electrode, a source electrode and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The P-type semiconductor layer is disposed on the barrier layer. The carrier providing layer is disposed on the sidewall of the P-type semiconductor layer and extends laterally away from the P-type semiconductor layer. The gate electrode is disposed on the P-type semiconductor layer. The source electrode and the drain electrode are disposed on the carrier providing layer and at two sides of the gate electrode. A method of forming an enhancement mode HEMT device is further provided.Type: ApplicationFiled: November 6, 2018Publication date: July 4, 2019Applicant: Nuvoton Technology CorporationInventors: Kuei-Yi Chu, Heng-Kuang Lin
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Publication number: 20190198653Abstract: A nitride semiconductor device is provided, including a substrate having a first surface and a second surface opposite to each other; a nucleation layer disposed on the first surface of the substrate; a doped nitride semiconductor layer disposed on the nucleation layer; a doped first buffer layer disposed on the doped nitride semiconductor layer; a channel layer disposed on the doped first buffer layer; a barrier layer disposed on the channel layer; a first electrode disposed on the barrier layer; a second electrode electrically connected to the doped nitride semiconductor layer; and a doped region disposed at least in a portion of the doped nitride semiconductor layer, wherein the doped region is extended from below the first electrode to be partially overlapped with the second electrode.Type: ApplicationFiled: November 12, 2018Publication date: June 27, 2019Applicant: Nuvoton Technology CorporationInventors: Kuei-Yi Chu, Heng-Kuang Lin, Jung-Tse Tsai, Shih-Po Lin, Chih-Wei Chen
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Patent number: 10276454Abstract: A semiconductor device, a semiconductor substrate and a method of forming the same are disclosed. The semiconductor substrate includes a first silicon-containing layer, a single crystalline III-V compound semiconductor layer and an amorphous III-V compound semiconductor layer. The first silicon-containing layer has a first region and a second region. The single crystalline III-V compound semiconductor layer is disposed on the first silicon-containing layer in the first region. The amorphous III-V compound semiconductor layer is disposed on the first silicon-containing layer in the second region.Type: GrantFiled: December 7, 2017Date of Patent: April 30, 2019Assignee: Nuvoton Technology CorporationInventors: Fang-Chang Hsueh, Heng-Kuang Lin
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Publication number: 20190096879Abstract: Provided is a semiconductor device including a substrate, a diode, a channel layer, a barrier layer, a first dielectric layer, a source, a drain, and a gate. The diode is disposed over the substrate or in the substrate. The channel layer is disposed over the diode. The barrier layer is disposed over the channel layer. The first dielectric layer is disposed over the barrier layer. The source is electrically connected to a first region of the diode by a first conductive via through the first dielectric layer, the barrier layer, and the channel layer. The drain is electrically connected to a second region of the diode by a second conductive via through the first dielectric layer, the barrier layer, and the channel layer. The gate is disposed over the channel layer between the source and the drain.Type: ApplicationFiled: September 20, 2018Publication date: March 28, 2019Applicant: Nuvoton Technology CorporationInventors: Chih-Wei Chen, Heng-Kuang Lin
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Patent number: 10217855Abstract: A semiconductor substrate and a semiconductor device are disclosed. The semiconductor substrate includes a base layer, a buffer layer disposed on the base layer, a channel layer disposed on the buffer layer, a barrier layer disposed on the channel layer, and a buried field plate region embedded in the channel layer. In an embodiment, the channel layer includes a two-dimensional electron gas (2DEG), and the buried field plate region is located below the two-dimensional electron gas.Type: GrantFiled: November 14, 2017Date of Patent: February 26, 2019Assignee: Nuvoton Technology CorporationInventors: Chih-Wei Chen, Heng-Kuang Lin
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Publication number: 20190051522Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a base, a buffer layer, a mask layer and a first GaN layer. The buffer layer is disposed on the base, wherein doped regions are disposed in a portion of the surface of the buffer layer. The mask layer is disposed on the buffer layer and located on the doped regions. The first GaN layer is disposed on the buffer layer and covers the mask layer.Type: ApplicationFiled: August 7, 2018Publication date: February 14, 2019Applicant: Nuvoton Technology CorporationInventors: Fang-Chang Hsueh, Heng-Kuang Lin
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Publication number: 20190035896Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first stacked structure, a second stacked structure, an isolation layer and a gate. The first stacked structure is disposed on a substrate, and includes a first GaN channel layer disposed on the substrate and having an N crystal phase and a first barrier layer disposed on the first GaN channel layer. The second stacked structure is disposed on the substrate, and includes a second GaN channel layer disposed on the substrate and having a Ga crystal phase and a second barrier layer disposed on the second GaN channel layer. The isolation layer is disposed between the first stacked structure and the second stacked structure. The gate is disposed on the first stacked structure, the isolation layer and the second stacked structure.Type: ApplicationFiled: May 28, 2018Publication date: January 31, 2019Applicant: Nuvoton Technology CorporationInventors: Chih-Wei Chen, Heng-Kuang Lin
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Publication number: 20190027426Abstract: Provided is a nitride semiconductor device including a substrate, a nucleation layer, a buffer layer, a channel layer, a first electrode, and a second electrode. The substrate has a first surface and a second surface opposite to the first surface. The nucleation layer, the buffer layer, the channel layer, and the barrier layer are sequentially disposed on the first surface of the substrate. The first electrode layer and the second electrode layer are disposed on the barrier layer. A first void penetrates through the substrate, the nucleation layer, the buffer layer, the channel layer, and the barrier layer and exposes a portion of the first electrode.Type: ApplicationFiled: July 19, 2018Publication date: January 24, 2019Applicant: Nuvoton Technology CorporationInventors: Kuei-Yi Chu, Heng-Kuang Lin
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Patent number: 10062766Abstract: A hetero-junction Schottky diode device includes a buffer layer, at least one channel layer, at least one barrier layer and a Schottky metal layer. The buffer layer is disposed on a substrate. The at least one channel layer is disposed on the buffer layer. The at least one barrier layer is disposed on the at least one channel layer. Besides, multiple strip openings are configured to penetrate through the at least one barrier layer and at least one channel layer. The Schottky metal layer is disposed on the at least one barrier layer, across the strip openings and fills in the strip openings.Type: GrantFiled: January 10, 2018Date of Patent: August 28, 2018Assignee: Nuvoton Technology CorporationInventors: Jung-Tse Tsai, Heng-Kuang Lin
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Publication number: 20180240877Abstract: A transistor including a buffer layer, a channel layer, a barrier layer, a superlattice structure, a gate, a source and a drain is provided. The buffer layer, the channel layer, the barrier layer, the superlattice structure and the gate are sequentially disposed on a substrate. The source and drain are disposed on the barrier layer and respectively at two sides of the superlattice structure, or on the channel layer and respectively at two sides of the barrier layer. The superlattice structure includes at least one first metal nitride layer and at least one second metal nitride layer stacked to each other. The average lattice constant of the superlattice structure is greater than that of GaN. The metal of each of the first and second metal nitride layers is at least one selected from the group consisting of Al, Ga and In. The first and second metal nitride layers are different.Type: ApplicationFiled: January 9, 2018Publication date: August 23, 2018Applicant: Nuvoton Technology CorporationInventors: Jung-Tse Tsai, Heng-Kuang Lin
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Publication number: 20180175186Abstract: A semiconductor substrate and a semiconductor device are disclosed. The semiconductor substrate includes a base layer, a buffer layer disposed on the base layer, a channel layer disposed on the buffer layer, a barrier layer disposed on the channel layer, and a buried field plate region embedded in the channel layer. In an embodiment, the channel layer includes a two-dimensional electron gas (2DEG), and the buried field plate region is located below the two-dimensional electron gas.Type: ApplicationFiled: November 14, 2017Publication date: June 21, 2018Applicant: Nuvoton Technology CorporationInventors: Chih-Wei Chen, Heng-Kuang Lin
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Publication number: 20180166339Abstract: A semiconductor device, a semiconductor substrate and a method of forming the same are disclosed. The semiconductor substrate includes a first silicon-containing layer, a single crystalline III-V compound semiconductor layer and an amorphous III-V compound semiconductor layer. The first silicon-containing layer has a first region and a second region. The single crystalline III-V compound semiconductor layer is disposed on the first silicon-containing layer in the first region. The amorphous III-V compound semiconductor layer is disposed on the first silicon-containing layer in the second region.Type: ApplicationFiled: December 7, 2017Publication date: June 14, 2018Applicant: Nuvoton Technology CorporationInventors: Fang-Chang Hsueh, Heng-Kuang Lin
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Patent number: 9711683Abstract: The present application discloses a semiconductor device comprising a crystalline substrate having a first region and a second region, a nuclei structure on the first region, a first crystalline buffer layer on the nuclei structure, a void between the second region and the first crystalline buffer layer, a second crystalline buffer layer on the first crystalline buffer layer, an intermediate layer located between the first crystalline buffer layer and the second crystalline buffer layer, and a semiconductor device layer on the second crystalline buffer layer.Type: GrantFiled: September 26, 2014Date of Patent: July 18, 2017Assignee: EPISTAR CORPORATIONInventors: Heng-Kuang Lin, Ya-Yu Yang
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Patent number: 9647102Abstract: A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas; a p+ III-V semiconductor layer, disposed over the second semiconductor layer; and a depolarization layer, disposed between the second semiconductor layer and the p+ III-V semiconductor layer, wherein the depolarization layer includes a metal oxide layer.Type: GrantFiled: March 9, 2016Date of Patent: May 9, 2017Assignee: Epistar CorporationInventors: Heng-Kuang Lin, Chien-Kai Tung