Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.

Abstract: The present invention relates to an extract of Salvia miltiorrhiza and/or an extract of Poncirus trifoliata for inhibiting obesity. In particular, the extract of Salvia miltiorrhiza and/or the extract of Poncirus trifoliata is/are prepared by solvent or supercritical fluid extraction. Specifically, the extract of Salvia miltiorrhiza and/or the extract of Poncirus trifoliata is/are effective in inhibiting lipid accumulation in adipocytes and slowing down body weight gain of the subject. More specifically, the extract of Salvia miltiorrhiza and/or the extract of Poncirus trifoliata can be used in combination with an extract of Curcuma longa, which exhibit improved effects in inhibiting lipid accumulation in adipocytes and slowing down body weight gain of the subject.

Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

Abstract: Semiconductor structures and processes are provided. A semiconductor structure of the present disclosure includes a first base portion and a second base portion extending lengthwise along a first direction, a first source/drain feature disposed over the first base portion, a second source/drain feature disposed over the second base portion, a center dielectric fin sandwiched between the first source/drain feature and the second source/drain feature along a second direction perpendicular to the first direction, and a source/drain contact disposed over the first source/drain feature, the second source/drain feature and the center dielectric fin. A portion of the source/drain contact extends between the first source/drain feature and the second source/drain feature along the second direction.

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

Abstract: A controller for a warning light is disclosed. The controller is composed of a housing, a light emitting element and a control unit. The control unit is in operable communication with the light emitting element of the controller and a light emitting element of a warning light. The controller instructs the light emitting element of the warning light and the light emitting element of the controller to display light in the same lighting mode, which allows vehicle operators to immediately know the lighting mode of the warning light by viewing the lighting mode of the controller.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: An antenna assembly comprising an antenna. The antenna includes: a substrate including a first surface and a second surface arranged opposite to each other; a first radiator disposed at the first surface and including two first radiation elements spaced apart from each other and connected to each other by a connector; and a second radiator disposed at the second surface and including a second radiation element disposed at an area of the second surface corresponding to an area of the first surface between the two first radiation elements. Each of the two first radiation elements and the second radiation element includes a current adjustment structure configured to adjust a current flow direction in the radiation element to which the current adjustment structure belongs.

Abstract: Semiconductor devices are provided. A semiconductor device includes a first well region having a first conductivity type, a second well region having a second conductivity type, a cell, and a pickup tap cell. The cell includes a first forksheet structure. The first forksheet structure includes a first transistor formed over the first well region, a second transistor formed over the second well region, and a first wall structure disposed on and extending along an interface between the first and second well regions. The first transistor and the second transistor are disposed on opposite sides of the first wall structure. The pickup tap cell includes a nanosheet structure. The nanosheet structure includes a pickup transistor formed over the second well region. Source/drain features of the first transistor and the pickup transistor have the second conductivity type, and source/drain features of the second transistor have the first conductivity type.

Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.

Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.

Abstract: Disclosed are a dual-motor multi-gear hybrid transmission system and a vehicle. The dual-motor multi-gear hybrid transmission system includes an engine, a first motor, a second motor, a first clutch, a second clutch, a first planet row, a second planet row, a first input shaft, a second input shaft, a third input shaft and a brake assembly. The first input shaft is connected to the engine through the first clutch. The second input shaft is connected to the engine through the second clutch, and the second input shaft is sleeved outside the first input shaft. The first motor is connected to the engine. The second motor is connected to the first planet row through the third input shaft. The brake assembly is configured to brake the first planet row and/or the second planet row.

Abstract: A method of forming low-k material is provided. The method includes providing a plurality of core-shell particles. The core of the core-shell particles has a first ceramic with a low melting point. The shell of the core-shell particles has a second ceramic with a low melting point and a low dielectric constant. The core-shell particles are sintered and molded to form a low-k material. The shell of the core-shell particles is connected to form a network structure of a microcrystal phase.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.