Patents by Inventor Henning Braunisch

Henning Braunisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220173489
    Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 2, 2022
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan
  • Patent number: 11348897
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan, Patrick Morrow, Kimin Jun, Brennen Mueller, Paul B. Fischer
  • Patent number: 11329358
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Patent number: 11329359
    Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan
  • Publication number: 20220130763
    Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: Ravindranath V. Mahajan, Zhiguo Qian, Henning Braunisch, Kemal Aygun, Sujit Sharan
  • Publication number: 20220102483
    Abstract: Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Thomas Sounart, Kaan Oguz, Neelam Prabhu Gaunkar, Aleksandar Aleksov, Henning Braunisch, I-Cheng Tung
  • Patent number: 11282800
    Abstract: An inductor in a device package and a method of forming the inductor in the device package are described. The inductor includes a first conductive layer disposed on a substrate. The inductor also has one or more hybrid magnetic additively manufactured (HMAM) layers disposed over and around the first conductive layer to form one or more via openings over the first conductive layer. The inductor further includes one or more vias disposed into the one or more via openings, wherein the one or more vias are only disposed on the portions of the exposed first conductive layer. The inductor has a dielectric layer disposed over and around the one or more vias, the HMAM layers, and the substrate. The inductor also has a second conductive layer disposed over the one or more vias and the dielectric layer.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Feras Eid, Georgios C. Dogiamis
  • Patent number: 11222847
    Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Ravindranath V. Mahajan, Zhiguo Qian, Henning Braunisch, Kemal Aygun, Sujit Sharan
  • Publication number: 20210408654
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing
  • Publication number: 20210408657
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing
  • Publication number: 20210408653
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing
  • Publication number: 20210408655
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Neelam Prabhu Gaunkar, Georgios Dogiamis, Telesphor Kamgaing, Henning Braunisch, Diego Correas-Serrano
  • Publication number: 20210407903
    Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Georgios Dogiamis, Henning Braunisch, Beomseok Choi, William J. Lambert, Stephen Morein, Ahmed Abou-Alfotouh, Johanna Swan
  • Publication number: 20210408652
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing
  • Publication number: 20210407934
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Neelam Prabhu Gaunkar, Georgios Dogiamis, Telesphor Kamgaing, Diego Correas-Serrano, Henning Braunisch
  • Publication number: 20210408656
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing
  • Publication number: 20210398895
    Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Georgios Dogiamis, Beomseok Choi, Henning Braunisch, William Lambert, Krishna Bharath, Johanna Swan
  • Publication number: 20210358855
    Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Applicant: Intel Corporation
    Inventors: Veronica Strong, Aleksandar Aleksov, Henning Braunisch, Brandon Rawlings, Johanna Swan, Shawna Liff
  • Publication number: 20210343635
    Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Applicant: Intel Corporation
    Inventors: Johanna Swan, Henning Braunisch, Aleksandar Aleksov, Shawna Liff, Brandon Rawlings, Veronica Strong
  • Patent number: 11133263
    Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Strong, Aleksandar Aleksov, Henning Braunisch, Brandon Rawlings, Johanna Swan, Shawna Liff