Abstract: A combination of a microphone and a sigma-delta A/D converter include at least one feedback loop, such as a DC feedback loop. The DC feedback loop provides the bias current for a junction FET of the microphone. In this way, the signal current from the FET can be injected directly into the input integrator of the sigma-delta A/D converter without the need of signal resistors in series with the FET.

Abstract: A quadrature device 1 for a communication device, receiver, transmitter, transceiver, telephone, mixer, modulator or demodulator comprises I and Q signal paths and corresponding signal paths components 2I, 2Q; 4I, 4Q; 9I, 9Q showing a mismatch. The device 1 comprises switching circuitry 3, 3?, 6, 3?, 3?? for data dependently exchanging the I and Q signals in the I and Q paths in order to improve adverse effects, such as reduction of leakage of quantisation noise from the image band to the signal band in a quadrature modulator. Even mismatch effects between digital to analog converters (DAC's) in a feedback path of a sigma delta (??) modulator are compensated.

Abstract: A combination of an electret microphone (1) and a sigma-delta A/D converter (9, 5, 7, 8). The sigma-delta A/D converter has a DC feedback loop (8) which provides the bias current (IDC) for the junction FET (2) of the electret microphone. In this way the signal current from the FET (2) can be injected directly into the input integrator (9) of the sigma-delta A/D converter without the need of signal resistors in series with the FET (2).

Abstract: A quadrature device 1 for a communication device, receiver, transmitter, transceiver, telephone, mixer, modulator or demodulator comprises I and Q signal paths and corresponding signal paths components 2I, 2Q; 4I, 4Q; 9I, 9Q showing a mismatch. The device 1 comprises switching means 3, 3′, 6, 3″, 3′″ for in particular data dependently exchanging the I and Q signals in said I and Q paths in order to improve adverse effects, such as reduction of leakage of quantisation noise from the image band to the signal band in a quadrature modulator. Even mismatch effects between digital to analog converters (DAC's) in a feedback path of a sigma delta (&Sgr;&Dgr;) modulator are compensated.

Abstract: The electric lamp has a vacuumtight seal (4) on the longitudinal axis (2) of a glass lamp vessel (1). An internal (12) and an external conductor (13) each have an end (14) inside the seal (4) and extend through a common axial region (5) of the seal (4) in a spaced apart manner. Several metal foils (11) arranged in a flat plane of the seal (4) extend parallel one to the other, in a transversal direction thereof. They have knife-shaped transversal edges (15) and are welded to the internal (12) and the external (13) conductors. The current conductors (10) constituted by the foils (11), the internal (12) and the external (13) conductors are able to conduct rather high currents. The lamp, nevertheless, is of a simple, strong and reliable construction.

Abstract: An information display device with adaptive scroll speed receives at its input (1a, 1b) messages in the form of bursts of information units. The display device comprises presentation apparatus (2), coupled to the input, comprising a display area (2.1) for displaying the messages. The presentation apparatus can scroll the information units through the display area at a specific scroll speed. The information display device further comprises a control signal generator (3) that generates a control signal which is derived from the average rate at which information units are received. The presentation apparatus control the scroll speed in response to the control signal.

Abstract: A display device comprising a display tube having a display screen with a pattern of phosphor elements. To reduce mislandings of electron beams, the display tube is accommodated within an external magnetic shield which is formed by one or more individual frames composed of bars of a magnetizable material and one or more excitable coils. The coils may be arranged, for example, alongside the frames.

Abstract: A circuit arrangement for igniting and operating a discharge lamp (La), provided withinput terminals (K1,K2) for connection to a DC voltage source,a commutator (COM) coupled to the input terminals and provided with terminals (K3,K4) for connecting the discharge lamp (La), for cornmutating a current through the discharge lamp (La),a branch A which is conducting in both directions at least for alternating current, of which branch a first end is connected to an input terminal (K2) and a further end is connected to the commutator (COM), and which branch comprises an inductive element L shunted by a branch B which comprises a unidirectional element (D),a branch C which connects a further input terminal to the commutator (COM), andan ignition circuit (S) for igniting the discharge lamp. According to the invention, the unidirectional element (D)is so included in the branch B that the branch B conducts a current at least immediately after ignition of the discharge lamp (La).

Abstract: A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3).

Abstract: When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

Abstract: An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

Abstract: An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.

Abstract: Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.