Abstract: A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and the third transistors are biased by a first voltage.

Abstract: A method of signal block reception with automatic gain control (AGC) for a receiver is disclosed. The receiver is configured for at least a sleep mode and an active mode. The signal blocks are non-adjacent in time, and each signal block is configured to be received in entirety using a valid AGC setting determined based on a previous signal block. The method comprises, when switching from the sleep mode to the active mode for continuous reception of a signal block, receiving a first set of samples of the signal block, determining an applicable AGC setting based on the first set of samples of the signal block, and receiving a second set of samples of the signal block using the applicable AGC setting determined based on the first set of samples. Corresponding apparatus, receiver, wireless communication device and computer program product are also disclosed.

Abstract: A radar sensing function is performed in a mobile communication device that operates in a Time Division Duplex (TDD) wireless communication system having an air interface that comprises a plurality of uplink symbol times associated with symbols transmitted in an uplink direction and a plurality of downlink symbol times associated with symbols transmitted in a downlink direction, and in which each transmitted symbol from a plurality of transmitted symbols has a corresponding cyclic prefix that is transmitted immediately before the corresponding transmitted symbol, and that is a repetition of an end part of the corresponding transmitted symbol. Information about a path delay between the mobile communication device and a receiver is used as one of one or more bases to determine a timing of a radar operation window having a duration that is shorter than a duration of a cyclic reception window of the receiver and comprising a radar signal transmission time and a radar backscatter reception period.

Abstract: A radar sensing function is performed in a mobile communication device that operates in a Time Division Duplex (TDD) wireless communication system having an air interface that comprises a plurality of uplink symbol times, a plurality of downlink symbol times, a plurality of TDD transmission direction transition periods, and a plurality of transition pairs of symbol times, wherein each of the transition pairs of symbol times comprises one of the uplink symbol times and one of the downlink symbol times, and each of the TDD transmission direction transition periods is associated with one of the plurality of transition pairs of symbol times and is immediately preceded by a first one of the uplink and downlink symbol times of the associated transition pair of symbol times and is immediately followed by a second one of the uplink and downlink symbol times of the associated transition pair of symbol times.

Abstract: A wireless device features a low-power, limited-functionality, narrowband, homodyne wakeup receiver with a free running local oscillator. This enables a very attractive combination of low power consumption and high selectivity. The network supports these receivers by adopting a wakeup message structure that supports oscillator frequency calibration, and that tolerates loss of parts of the signal spectrum. Wakeup signals are transmitted frequently to allow the wakeup receivers (whether targeted by a wakeup signal or not) to calibrate their LO frequencies. The frequencies of the wakeup signals can be constant, or follow a hopping pattern for increased immunity to interference. The wakeup signals can use multiple carriers to increase robustness to loss of parts of the signal spectrum, particularly near the LO frequency in a homodyne receiver. The carriers use amplitude modulation (OOK), with either different or equal sequences.

Abstract: A transmitter and method therein for transmitting a signal to a receiver in a wireless communication system are disclosed. The transmitter is configured to modulate a signal using two different modulations, a combination of binary amplitude shift keying, ASK, and binary frequency shift keying, FSK, and transmit the modulated signal.

Abstract: A differential combiner circuit (200) comprises three ports each has two terminals (1a, 1b, 2a, 2b, 3a, 3b). The differential combiner circuit (200) further comprises a first sub-circuit comprising a first inductor (L1) connected between the first terminals (1a, 2a) of the first and second ports, and a first capacitor (C1) connected between the first terminals (2a, 3a) of the second and third ports; a second sub-circuit comprising a second inductor (L2) connected between the second terminals (1b, 2b) of the first and second ports, and a second capacitor (C2) connected between the second terminals (2b, 3b) of the second and third ports.

Abstract: A limited-function, low-power wakeup receiver is based on frequency shift keying (FSK), avoiding the inherent problems of AM demodulation such as non-linearity of the amplitude detector. The FSK detector is easily realized in the digital domain. Due to the time discrete nature of FSK signals, the detector has a periodic response in frequency, allowing the signal to be demodulated at different offsets from the center frequency. The relaxed accuracy demands on the local oscillator frequency avoid the need for a power-hungry phase locked loop (PLL) circuit. To avoid potential loss if a signal coincides with one of the regular sensitivity nulls, the network at least occasionally transmits an FSK wakeup signal at a slightly shifted frequency, so at least one of the FSK wakeup signals will be received. Transmitting multiple frequency-shifted signals improves the likelihood of reception.

Abstract: A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.

Abstract: An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals and to provide first and second outputs based on the first and second input signals. A difference in pulse length between signals provided at the first and second outputs is indicative of the phase difference between the first and second input signals. The apparatus also comprises first and second time-to-digital converters (TDCs) each configured to receive one of the signals provided by the PFD and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC, wherein pulse length modification may comprise pulse length shrinking or pulse length extension.

Abstract: A frequency detector (200) and method therein for measuring and tuning a frequency of a controlled oscillator are disclosed. The frequency detector (200) comprises a pulse generator (210) for generating sampling pulses; a sample circuitry (220) for sampling output states of the controlled oscillator (180); and a digital processing unit (230). The sample circuitry (220) is configured to sub-sample the output states of the controlled oscillator (180) at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator. The digital processing unit (230) is configured to calculate a frequency offset of the oscillator based on the sampled states and generate a control signal based on the frequency offset to tune the frequency of the oscillator.

Abstract: A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103).

Abstract: A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.

Abstract: A transmitter circuit has a signal input for receiving an analog input signal and a local oscillator (LO) input for receiving an LO signal. A mixer circuit has a first input, a second input, and an output. The second input of the mixer circuit is connected to a signal input of the transmitter circuit. A PA circuit has an input connected to the output of the mixer circuit, and an output. A control circuit generates a phase-control signal and a gain-control signal in response to an envelope of the analog input signal. A phase-control circuit generates a phase-adjusted LO signal in response to the LO signal and the phase-control signal and supplies the phase-adjusted LO signal to the first input of the mixer circuit. A gain-control circuit controls a gain of the transmitter circuit in response to the gain-control signal.

Abstract: An example of a receiver circuit is disclosed. The receiver circuit comprises an input for receiving a radio frequency signal, an output for providing an output signal of the receiver circuit, a receive path, wherein the receive path is connected between the input and the output of the receiver circuit, and a feedback path, wherein an input of the feedback path is connected to the output of the receiver circuit. The receiver circuit also comprises a transformer, wherein an output signal of the feedback path is combined with the received radio frequency signal in the receive path to form a first signal. The receive path comprises a first mixer for downconverting the first signal by a local oscillator frequency, and an amplifier for amplifying the downconverted first signal. The feedback path comprises a second mixer for upconverting a signal in the feedback path by said local oscillator frequency.

Abstract: A time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The TDC circuitry comprises multiple constituent TDCs, a reference signal provider, and a digital signal combiner. Each TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal. The reference signal provider is configured to provide the respective constituent reference signals to each of the TDCs. In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals.

Abstract: A communication device comprises a modem and a transceiver, wherein the modem comprises digital baseband circuitry for generating a digital baseband signal for transmission, and the transceiver is configured to receive the digital baseband signal from the modem and to generate therefrom a radiofrequency signal for transmission by the communication device. The communication device controls the modem to operate in a first mode, and controls the modem to operate in a second mode. The first mode is a radar mode in which the modem generates radar baseband signals for transmission as one or more radar radiofrequency signals by the transceiver, and the second mode is a communication mode in which the modem generates information-containing baseband signals for transmission by the transceiver.

Abstract: On-chip multi-band equalizers for adjusting signal strength for a receiver receiving multi-band frequency signals are provided. An example multi-band equalizer comprises multiple series connected tapped LC resonators. The tapped LC resonator may be capacitive tapping or inductive tapping, where both frequency and gain of the frequency bands of interest may be programmed by tuning the capacitances of the programmable capacitors and/or selecting the tapped-out terminals of the inductors. The multi-band equalizer may be connected to a signal node, for instance between two amplifiers in the receiver.

Abstract: A radar-enabled wireless communication device (12) is configured for exchanging communication signals with a wireless communication network (10) and for performing radar transmissions for surrounding-environment sensing. The device (12) classifies radar beam directions (30) as restricted or unrestricted, based on known or estimated interference with Uplink (UL) reception operations of the network (10) and adapts its radar transmissions based on the classifications. Classification operations may be autonomous, without requiring explicit network support, or may be based on one or radio network nodes (22) of the network (10) performing supporting procedures. Updating the classifications depends on, for example, one or more triggering conditions, such as changes in the position or orientation of the device (12), transmit-frequency changes, and changes in ambient conditions, such as the presence or intensity of rain.

Abstract: An analog PLL employs digital circuitry for calibration and characterization, precisely setting and maintaining the bandwidth of the PLL. A digital calibration circuit calibrates the value of the resistor or capacitor in the loop filter to yield a desired RC product. A digital control circuit reads time-to-digital converters (TDC) digitizing the length of the CU and CD pulses from the phase-frequency detector (PFD) to the charge pump (CP) during a frequency change. These pulse lengths are summed to yield a measured integral CP current. The control circuit determines an integral CP current that yields a desired bandwidth, regardless of the VCO tuning sensitivity, based on the calibrated RC product. The CP current is then adjusted by the ratio of determined integral CP current to the measured integral CP current. The digital circuits are only activate initially, and occasionally to compensate for temperature drift or upon a significant frequency change.