Abstract: A method and apparatus for debugging programs in a distributed environment, such as a set of heterogeneous hardware processors (integrated circuits or In-Circuit Emulators), and/or software-based simulators. In one embodiment, the method comprises identifying a plurality of processes; initializing each of the processes; executing with a single thread of control among the processes; and continuously cycling among the processes to obtain status information. A computer program and apparatus for implementing the aforementioned methodology are also disclosed.

Abstract: Aspects of the present invention relate to nucleotide and amino acid sequences of oocyte factors for altering ovarian follicular growth in vivo or in vitro. The present invention also concerns novel homodimeric and heterodimeric polypeptides and their use for altering mammalian ovarian follicular growth in vivo or in vitro.

Abstract: A process for solvent extraction of oils, in an extraction chamber, comprises the formation of a solvent mist with significant adiabatic cooling, whereby a pressure difference between the solvent inlet and outlet of the extraction chamber drives the solvent mist through the raw oil bearing. The solvent is fed to the extraction chamber at pressures exceeding atmospheric pressure, and the outlet of the extraction chamber is subject to a partial vacuum. An apparatus for solvent extraction comprises an extraction chamber for receiving oil bearing raw material therein, said extraction chamber comprising a solvent spray injection system connected via an inlet to a high pressure solvent feed circuit portion, said extraction chamber further connected via an outlet to a low pressure circuit portion connected to a gas recovery vacuum pump system.

Abstract: A wound covering includes a loop member including a peripheral wall that has an upper edge, a lower edge, an inner surface and an outer surface. The loop member defines an opening. A screen is attached to the loop member such that the screen extends across the opening. The screen comprises an air permeable and flexible material. A panel is attached to and extends along the peripheral wall of the loop member such that the panel does not extend over the opening. The panel comprises a flexible material having an upper surface and a lower surface. The lower surface faces the same direction as the lower edge of the loop member. An adhesive is positioned on the lower surface of the panel. The panel may be attached to a skin surface such that the loop member extends around a wound on the skin surface.

Abstract: A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external contacts. The monitor uses a separate circular buffer to continuously store, in real-time, data traces from each of one or more internal processor buses. Upon the occurrence of a trigger condition, storage stops and a trace is preserved. Trigger conditions can depend on events occurring on multiple buses and are downloaded via an interface from an external device. Data traces are uploaded via the interface to an external device for evaluation of processor operation.

Abstract: A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external contacts. The monitor uses a separate circular buffer to continuously store in real-time, data traces from each of one or more internal processor buses. Upon the occurrence of a trigger condition, storage stops and a trace is preserved. Trigger conditions can depend on events occurring on multiple buses and are downloaded via an interface from an external device. Data traces are uploaded via the interface to an external device for evaluation of processor operation.

Abstract: Aspects of the present invention relate to nucleotide and amino acid sequences of oocyte factors for altering ovarian follicular growth in vivo or in vitro. The present invention also concerns novel homodimeric and heterodimeric polypeptides and their use for altering mammalian ovarian follicular growth in vivo or in vitro.

Abstract: A process for solvent extraction of oils, in an extraction chamber, comprises the formation of a solvent mist with significant adiabatic cooling, whereby a pressure difference between the solvent inlet and outlet of the extraction chamber drives the solvent mist through the raw oil bearing. The solvent is fed to the extraction chamber at pressures exceeding atmospheric pressure, and the outlet of the extraction chamber is subject to a partial vacuum. An apparatus for solvent extraction comprises an extraction chamber for receiving oil bearing raw material therein, said extraction chamber comprising a solvent spray injection system connected via an inlet to a high pressure solvent feed circuit portion, said extraction chamber further connected via an outlet to a low pressure circuit portion connected to a gas recovery vacuum pump system.

Abstract: The present invention relates to nucleotide sequences which are involved in increasing or decreasing mammalian ovulation rate. In particular, the invention broadly concerns novel mutations in a gene which is involved in increasing the ovulation rate in heterozygous female mammals; these mutations cause sterility in homozygous female mammals. Knowledge of the mutated gene sequence can be applied to a test for identifying heterozygous of homozygous female and male mammals carrying the mutated gene. This knowledge of the biological function of the gene and its mutations can also be utilised to increase or decrease the ovulation rate of female mammals, or to induce sterility or reduced fertility in female mammals.

Abstract: A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external contacts. The monitor uses a separate circular buffer to continuously store, in real-time, data traces from each of one or more internal processor buses. Upon the occurrence of a trigger condition, storage stops and a trace is preserved. Trigger conditions can depend on events occurring on multiple buses and are downloaded via an interface from an external device. Data traces are uploaded via the interface to an external device for evaluation of processor operation.

Abstract: A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external contacts. The monitor uses a separate circular buffer to continuously store, in real-time, data traces from each of one or more internal processor buses. Upon the occurrence of a trigger condition, storage stops and a trace is preserved. Trigger conditions can depend on events occurring on multiple buses and are downloaded via an interface from an external device. Data traces are uploaded via the interface to an external device for evaluation of processor operation.

Abstract: A method and an apparatus 10 for analyzing the operation of a circuit, such as but not limited to the circuit 20, and for allowing one to quickly and efficiently create an electrical and/or electronic circuit.

Abstract: A digital signal processor (DSP) architecture which allows the DSP Multiply-Accumulator (MAC) to be used for special fixed functions during those times when the programmable portions of the DSP are not using the MAC circuitry. During the idle times, the DSP processor gives control of the MAC to the fixed function circuit. The fixed functions provided by the fixed function circuit can include digital filters, including a Finite Impulse Response filters (FIR), an Infinite Impulse Response (IIR) filter, or an oversampling filter associated with a sigma-delta converter. The DSP may, under program control, set up specific parameters for the fixed function, provide parameters to the fixed function parameter memory, or obtain results from the fixed function. Parameters for the fixed function circuit include the type of filter, the number of taps and the filter coefficients. For a decimation filter, the fixed function parameters can also include the decimation factor.

Abstract: A method and apparatus for enhancing the performance of a multi-stage pipeline in a digital processor. In one aspect, the stalling of multi-word (e.g. long immediate data) instructions on the word boundary is prevented by defining oversized or “atomic” instructions within the instruction set, thereby also preventing incomplete data fetch operations. In another aspect, the invention comprises delayed decode of breakpoint instructions within the core so as to remove critical path restrictions in the pipeline. In yet another aspect, the invention comprises a multi-function register disposed in the pipeline logic, the register including a bypass mode adapted to selectively bypass or “shortcut” subsequent logic, and return the result of a multi-cycle operation directly to a subsequent instruction requiring the result. Improved data cache integration and operation techniques, and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.

Abstract: A method and apparatus for debugging programs in a distributed environment, such as a set of heterogeneous hardware processors (integrated circuits or In-Circuit Emulators), and/or software-based simulators. In one embodiment, the method comprises identifying a plurality of processes; initializing each of the processes; executing with a single thread of control among the processes; and continuously cycling among the processes to obtain status information. A computer program and apparatus for implementing the aforementioned methodology are also disclosed.

Abstract: Arrangements for controlling a data switching network fabric and for synchronizing duplicate modules of such a fabric. A control complex, for determining new virtual connections to be established, and for disconnecting existing virtual connections, is connected through data links to the network fabric of a data switch. The network fabric has internal control processors. The control complex communicates with these processors by sending control packets over a dedicated internal ATM link and virtual connections to these internal processors to control their establishment and disconnection of user virtual connections. Duplicate modules of the data switching fabric receive identical packets and, when synchronized, transmit identical packets at the same time. The synchronization process is implemented by data links between the control processors of the duplicate fabrics to report progress on the step by step synchronization of internal queues.

Abstract: Arrangements for controlling a data switching network fabric and for synchronizing duplicate modules of such a fabric. A control complex, for determining new virtual connections to be established, and for disconnecting existing virtual connections, is connected through data links to the network fabric of a data switch. The network fabric has internal control processors. The control complex communicates with these processors by sending control packets over a dedicated internal ATM link and virtual connections to these internal processors to control their establishment and disconnection of user virtual connections. Duplicate modules of the data switching fabric receive identical packets and, when synchronized, transmit identical packets at the same time. The synchronization process is implemented by data links between the control processors of the duplicate fabrics to report progress on the step by step synchronization of internal queues.