Abstract: A system and method checks whether messages exchanged between first and second modules are being lost or gained. The first module has a request counter and a capture register. The second module has a request accumulator and a capture register. As the first module issues and receives messages, it increments and decrements its request counter. As the second module receives and issues messages, it increments and decrements its request accumulator. To check for lost or gained messages, the first module copies the current value of its request counter into its capture register, and issues a marker to the second module. The first module decrements its capture register in response to receiving post-marker messages, but does not increment its capture register. Upon receipt of the marker, the second module copies the current value of its request accumulator into its capture register, and returns the marker to the first module. When the first module receives the marker, it stops decrementing its capture register.

Abstract: A technique and system for manipulating, converting or adapting datagram headers as required during traverse from one interface of a networking device to another, by novel clocked micro-sequencing and selection amongst input and output FIFO data streams, through dividing input serial data streams into small groups of FIFO input data streams and feeding the groups parallely into a matrix of a multilane highway of header unit input data, constant data pattern and computational unit busses controlled by such micro-sequencing so as to enable such processing of packet datagram headers and the like at very high wire speed, but using low clock speeds, and in a scalable manner.