Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped

Abstract: Carbon has many advantageous uses as a sacrificial material in the fabricating thin-film storage transistors, such as those organized as NOR memory strings. In one implementation, the carbon layers are replaced by heavily doped n-type polysilicon source and drain regions at a late step during device fabrication. As a result, many high temperature steps within the fabrication process may now be carried out without concern for thermal diffusion from the heavily doped polysilicon, thus allowing phosphorus to be used as the n-type dopant.

Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

Abstract: By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (“FeFETs”), thereby providing a very high-speed, high-density memory array.

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, N2O, and NH3 gas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.

Abstract: A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a moncrystlline semiconductor substrate.

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.