Abstract: An image reading apparatus comprises a vertical type paper feed unit which feed paper into a printing unit, and a discharge unit which contains the paper discharged from the printing unit. The paper feed unit and the discharged unit are arranged in a vertical direction to the printing unit, which will allow the floor surface projection area to be reduced. Further, the paper is conveyed into one of discharge trays in accordance with its paper size. Thereby, the larger size paper is discharged underside the smaller size paper, accordingly, it does not occur for the paper discharged to the upper discharge tray to shield the paper on the lower stage discharge tray from the visual angle. Also, the confirmation of paper discharge and taking out can be easily carried out irrespective of the paper size.

Abstract: An image reading apparatus comprises a vertical type paper feed unit which feed paper into a printing unit, and a discharge unit which contains the paper discharged from the printing unit. The paper feed unit and the discharged unit are arranged in a vertical direction to the printing unit, which will allow the floor surface projection area to be reduced. Further, the paper is conveyed into one of discharge trays in accordance with its paper size. Thereby, the larger size paper is discharged underside the smaller size paper, accordingly, it does not occur for the paper discharged to the upper discharge tray to shield the paper on the lower stage discharge tray from the visual angle. Also, the confirmation of paper discharge and taking out can be easily carried out irrespective of the paper size.

Abstract: An image producing apparatus having a function to display information concerning documentation control, comprises display units in paper stack along with display units in a main body of the apparatus. The display unit placed nearby the paper stack displays information concerning documentation control of the paper discharged into the paper stack, and display unit in the main body displays information concerning documentation control of the image data stored in a memory. The apparatus has the capabilities of changing the displayed contents easily without replacing the labels and of confirming the situation of outputted images. Furthermore, the document data can be controlled based on operations in an operation unit of the main body of the apparatus.

Abstract: An image producing apparatus comprises a paper passage route which conveys paper selectively from a manual paper-feed unit and a paper feed unit, and conveys paper discharged from a print unit, and an image reading unit which reads out images of a document conveyed in the paper passage route. In a usual state, printed output is produced on the paper contained in the paper feed unit of a body, and the manual paper-feed unit is kept vacant, then, there is no need to take out the paper in the case of loading the document to be read out in the manual paper-feed tray. Moreover, the apparatus does not have a paper feed tray, a discharge tray and a paper passage route used only for image reading, which can decrease manufacturing costs, and besides, makes it possible to take up less installation space.

Abstract: A method and apparatus for configuring a single point arbitration scheme for a commonly accessed communication bus using bus master devices with arbitration control circuitry included therein. Bus master devices including arbitration control circuitry may be connected to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same connections to the arbitration control bus provide signals which are decoded at each bus master device to provide a configuration status which indicates whether other bus master devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the arbitration.

Abstract: An image producing apparatus comprises a table which is provided over the upper surface of a top plate in a body thereof for placing an external device. Besides, the apparatus also comprises a connector unit which is located adjacent to the table for connection to the external device. Thus, the connection of the external device will be simplified, and besides, the external device can be operated with ease when the external device is connected to the apparatus. Furthermore, the apparatus is provided with a stationary swiveling mechanism, so that a user can easily turn a side of the body, where a sheet of paper is jammed, to the front.

Abstract: An apparatus is provided for conducting solid phase oligomer synthesis. The apparatus includes a reaction vessel in which a solid phase support is contained. The reaction vessel has a top opening through which gases and solvents can be delivered by way of a series of conduits and valves. The reaction vessel is interconnected through a bottom opening therein and through a series of conduits and valves with a vessel or series of vessels containing a reagent or series of reagents, respectively, required for the synthetic reaction. The reagent vessel serves a both a source of reagent delivered to the reaction vessel and as a repository for unused reagent returned thereto from the reaction vessel. Reagent delivery and mixing is gas-driven using an associated source of an inert gas.

Abstract: A method and apparatus for configuring a centralized arbitration scheme for a commonly accessed communication bus using arbiter devices with arbitration control circuitry included therein. The arbiter devices, each of which is associated with a separate bus master device, include arbitration control circuitry and are coupled to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same arbiter device connections to the arbitration control bus provide signals which are decoded via arbitration configuration circuitry on each device to provide a configuration status indicating whether other devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the required arbitration.

Abstract: An apparatus and method are provided for maintaining lock characteristics while providing selective access to a cache during lock cycles. To guarantee that only one master accesses memory at a time, locked cycles are always passed to the internal arbitration unit of the memory controller, even if they are cache hits. If the local bus is not granted or cannot be guaranteed that it will be granted the bus for the locked cycle, the cycle is cancelled.

Abstract: A cache memory is provided which adjusts its response to addresses in accordance with the number of identical cache memory cards installed in the motherboard. Upon its installation in the motherboard a card is informed of its status as a master or a slave. As long as a slave is not installed the master responds to processor accesses over the entire address range of the computer. When a slave is installed a signal is sent to the master. Circuitry on the memory cards restricts the master response to half the address range. The slave being informed of its status restricts its response to the other half of the address range.

Abstract: The cache controller of a second level cache in an Intel Pentium processor based computer system contains test circuitry that allows reading and writing directly into all tag RAM databit locations. This circuitry responds to a modified External Address Strobe (EADS#) command to invoke the tag test cycle. The EADS# command is normally used in a SNOOP read cycle by the system. In a SNOOP cycle, the main memory controller invokes the EADS# command to request the first level (L.sub.1) and second level (L.sub.2) caches for modified information stored in those caches. In the tag test cycle the EADS# command line is held down twice as long as it would in a normal SNOOP read Cycle. Because of its added length, the SNOOP cycle circuits in the L.sub.2 cache ignore the command on the EADS# command line. However, the tag RAM test circuitry in the L.sub.