Patents by Inventor Henry J. Fulford
Henry J. Fulford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9991210Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: GrantFiled: July 25, 2016Date of Patent: June 5, 2018Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Publication number: 20160336276Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 9406623Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: GrantFiled: October 6, 2014Date of Patent: August 2, 2016Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Publication number: 20150021707Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: ApplicationFiled: October 6, 2014Publication date: January 22, 2015Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 8853833Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: GrantFiled: June 13, 2011Date of Patent: October 7, 2014Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Publication number: 20120313691Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: ApplicationFiled: June 13, 2011Publication date: December 13, 2012Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 5538923Abstract: The quality of both a gate oxide and a tunnel oxide in a P-well of a CMOS EEPROM process is improved by growing and subsequently annealing in-situ a gate oxide. A photoresist layer is then applied and defined to expose regions of the gate oxide which are then etched to expose the surface of the semiconductor, and after which the photoresist layer is removed. Subsequently, the remaining gate oxide is partially etched to reduce the thickness of the gate oxide and to remove any native oxide which may have formed over the exposed semiconductor surface. Finally, a tunnel oxide is grown upon the exposed semiconductor surface. The quality of this tunnel oxide is dramatically improved due to the in-situ anneal of the gate oxide, even though the gate oxide (in the region of the tunnel oxide) is totally removed before tunnel oxide growth. Furthermore, the re-oxidized gate oxide which was not entirely removed before tunnel oxide growth also exhibits higher breakdown voltages.Type: GrantFiled: May 27, 1994Date of Patent: July 23, 1996Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Henry J. Fulford, Jr.
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Patent number: 5362685Abstract: The quality of both a gate oxide and a tunnel oxide in a P-well active area of a CMOS EEPROM process is improved by reducing the field edge pullback arising from wet chemical etch steps prior to the growth of the gate and tunnel oxides. A first oxide is grown, and an implant is performed through the first oxide to form an implanted layer. The surface of the first oxide is then cleaned without removing all of the first oxide overlying the implanted layer. An anneal step then activates the implanted layer to form a heavily-doped region, after which the remaining first oxide is then removed. A second oxide is then grown, and a region of the second oxide is removed overlying the heavily-doped region. Lastly, a tunnel oxide is grown over the heavily-doped region while re-oxidizing the second oxide to form a gate oxide thicker than the tunnel oxide.Type: GrantFiled: October 29, 1992Date of Patent: November 8, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Henry J. Fulford, Jr., Jay J. Seaton
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Patent number: 5350491Abstract: A method is disclosed for removing oxide from the surface of a semiconductor body having a thick oxide and an adjoining thin oxide, without subjecting the surface to significant over-etching and thus avoiding degradation of the surface of the semiconductor body. A photoresist layer is first deposited covering the thin oxide. The thick oxide is then etched for a period of time so that a portion of the thick oxide remains, and has a thickness comparable to that of the thin oxide. The photoresist layer covering the thin oxide is next removed without appreciably etching either the remaining portion of the thick oxide or the thin oxide. Finally, the thin oxide and the remaining portion of the thick oxide are removed, without appreciably over-etching the surface of the semiconductor body.Type: GrantFiled: September 18, 1992Date of Patent: September 27, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Henry J. Fulford, Jr., Mark I. Gardner
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Patent number: 5350492Abstract: A method is disclosed for removing oxide from the surface of a semiconductor body having a thick oxide and an adjoining nitride-covered thin oxide, without subjecting the surface to significant over-etching and thus avoiding degredation of the surface of the semiconductor body. The thick oxide is first etched for a period of time so that a portion of the thick oxide remains, and has a thickness comparable to that of the thin oxide. The nitride covering the thin oxide is next removed without appreciably etching either the remaining portion of the thick oxide or the thin oxide. Finally, the thin oxide and the remaining portion of the thick oxide are removed, without appreciably over-etching the surface of the semiconductor body.Type: GrantFiled: September 18, 1992Date of Patent: September 27, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Steven C. Hall, Mark I. Gardner, Henry J. Fulford, Jr.
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Patent number: 5316981Abstract: The quality of both a gate oxide and a tunnel oxide in a P-well of a CMOS EEPROM process is improved by growing and subsequently annealing in-situ a gate oxide. A photoresist layer is then applied and defined to expose regions of the gate oxide which are then etched to expose the surface of the semiconductor, and after which the photoresist layer is removed. Subsequently, the remaining gate oxide is partially etched to reduce the thickness of the gate oxide and to remove any native oxide which may have formed over the exposed semiconductor surface. Finally, a tunnel oxide is grown upon the exposed semiconductor surface. The quality of this tunnel oxide is dramatically improved due to the in-situ anneal of the gate oxide, even though the gate oxide (in the region of the tunnel oxide) is totally removed before tunnel oxide growth. Furthermore, the re-oxidized gate oxide which was not entirely removed before tunnel oxide growth also exhibits higher breakdown voltages.Type: GrantFiled: October 9, 1992Date of Patent: May 31, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Henry J. Fulford, Jr.
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Patent number: 5296411Abstract: A high-quality tunnel oxide, suitable for EEPROM devices, is formed upon a surface region of a semiconductor body over a heavily-doped N+ layer by first oxidizing the semiconductor body to form an oxide upon the surface region of the semiconductor body over the heavily-doped N+ layer. Next, the semiconductor body is annealed, under a gettering ambient, to densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent. The semiconductor body is then oxidized, under an oxidizing ambient, to thicken the oxide, after which it is annealed for a second time, this time under an oxidizing ambient containing nitrogen, to further thicken the oxide and to form a surface layer therein containing a concentration of nitrogen. Tunnel oxides thus fabricated exhibit dramatically improved time-to-breakdown characteristics compared to tunnel oxides processed without such a nitrogen anneal.Type: GrantFiled: April 28, 1993Date of Patent: March 22, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Henry J. Fulford, Jr.