Abstract: This application discloses a computing system implementing tools and mechanisms to synchronize multiple layouts for a circuit design during the layout process. The tools and mechanisms can implement multiple communicating kernels, each to manage at least one of the layouts. In response to an alteration of one of the layouts, the kernels can communicate with each other, so that the kernel corresponding to the unaltered layout can automatically augment corresponding layouts for the circuit design to synchronize with the altered layout. At least one of the layouts can include a 3-dimensional layout representation of the circuit design, the tools and mechanisms can perform 3-dimensional design rule checking based on mechanical constraints and 3-dimensional solid component models in response to alterations to a 2-dimensional layout representation of the circuit design.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: This application discloses a computing system implementing tools and mechanisms to synchronize multiple layouts for a circuit design during the layout process. The tools and mechanisms can implement multiple communicating kernels, each to manage at least one of the layouts. In response to an alteration of one of the layouts, the kernels can communicate with each other, so that the kernel corresponding to the unaltered layout can automatically augment corresponding layouts for the circuit design to synchronize with the altered layout. At least one of the layouts can include a 3-dimensional layout representation of the circuit design, the tools and mechanisms can perform 3-dimensional design rule checking based on mechanical constraints and 3-dimensional solid component models in response to alterations to a 2-dimensional layout representation of the circuit design.

Abstract: Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract: Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed.

Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.

Abstract: Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed.

Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.

Abstract: An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and allows special behavior of the automatic and interactive routing routines that operate on the escapes. Still further, an escape outline may be employed to improve the creation of escape traces by automatic routing tools. The use of pseudo-pins for netline optimization also is provided. Breakouts in a printed circuit board design are analyzed, and their respective endpoints are identified. These endpoints are then employed in a netline optimization analysis instead of the pins from which the breakouts originate. In this manner, the endpoints of the breakout are used as pseudo-pins to substitute for the actual pins of a component.

Abstract: A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.

Abstract: Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed.

Abstract: Various implementations of the invention provide a method for dynamically determining a layer bias. In various implementations, the layer bias may be employed to determine placement locations for a trace within an electrical device layout design. The trace providing for the electrical connection of components or pins within the layout design. With various implementations of the invention, a layer within the layout design is partitioned into regions, selected regions having a bias. As events or alterations to the layout design occur, the corresponding bias for the selected regions is updated to reflect any changes in bias occurring due to the event or alteration. With other implementations of the invention, processes, machines, or manufactures are provided that dynamically determine a layer bias. The dynamically determined layer bias may be incorporated into a layer bias heuristic employed by for example, an automated trace routing tool.

Abstract: A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Abstract: PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate data structures. Those structures may be edited by users at separate clients during concurrent editing sessions. Profile data for each of multiple users specifies logical design data elements accessible by, and PCB design software to be provided to, that user. The PCB design software may be plug-ins executable within a web browser at a client, and the client computers may communicate with the database via the Internet. Layout data may also be stored in the database, with elements of the layout data mapped to elements of the logical design data. Constraint data may also be stored in the database, with elements of the constraint data being mapped to elements of the layout data.

Abstract: Multiple users simultaneously edit at least a portion of a printed circuit board (PCB) design. The PCB design portion is transmitted to first and second clients for graphical display at each of the clients. A first protection boundary is associated with an area of the PCB design being edited at the first client. A second protection boundary is associated with an area of the PCB design being edited at the second client. The first and second protection boundaries are displayed at each of the first and second clients. A request from one of the clients to edit an object within a region bounded by a protection boundary associated with the other client is rejected. The protection boundary may surround a user's cursor. The size of the boundary may increase based on editing activity by a user in an area of a PCB design.