Abstract: In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift register out. A storage unit is provided with a plurality of storage location lengths. The boundary scan signal groups are stored in a location having a suitable storage capacity. The command that transfers the boundary scan signal group includes a parameter identifying the relevant location. The scan control unit, upon receiving the command, transfers the entire boundary scan signal group as a result this command even if several transfers through the shift register out are required.

Abstract: In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with the scan controller, to determine whether one of several possible signal groups is present in the received data stream. The test and debug unit generates a series of numbers, each number corresponding to a preselected signal groups. The corresponding field in the received data stream is decoded to provide a series of output signals, each output signal corresponding to one group. The output signals of the decoder are compared to corresponding numbers of the expected value. When a signal from the decoder unit is found to correspond to one of the selected data number, the poll operation is a success.

Abstract: In a JTAG test and debug environment, the parameters that are accessed by command include a delay parameter. The delay parameter prevents the subsequent command from being executed until both the original command has been executed and the clock cycles indicated by the delay parameter have been completed. Because the time delay is included as a parameter identified by the command, the delay parameter can be programmed.

Abstract: A method for debugging a target processor is provided that includes storing a plurality of data values to be sent to the target processor in a first-in first-out (FIFO) buffer unit, saving a copy of an address in a read address counter of the FIFO buffer unit, wherein the address is that of an initial data value of a sequential portion of the plurality of data values, performing a transfer operation to send the sequential portion to the target processor, wherein the read address counter is incremented as each data value is sent. The method also includes resetting the read address counter with the copy of the address if the transfer operation fails and performing the transfer operation again.

Abstract: An electronic system includes electronic circuitry to be tested having serial scan shift register latches, and a serial scan generator embedded in the electronic system upon manufacture and connected to the serial scan shift register latches of the electronic circuitry to facilitate testing. The electronic system may consist of a single printed circuit board mounting both the electronic circuitry and the serial scan generator. The electronic system may consist of a single semiconductor chip carrier mounting both the electronic circuitry and the serial scan generator, are both mounted on said single semiconductor chip carrier. The electronic system may further include a detachable second serial scan generator. The serial scan generator preferably operates slower than the detachable second serial scan generator. The electronic system may further include a disabling terminal disabling the serial scan generator upon attachment of the detachable second serial scan generator.

Abstract: An electronic system for use with a host computer. The system includes electronic circuitry including a first semiconductor chip generally operable for a first function and also adapted for input and output of emulation signals. This is combined with emulation circuitry including a second semiconductor chip adapted for connection to the host computer. The emulation circuitry is connected to the electronic circuitry to generate emulation signals to input to the electronic circuitry and to accept emulation signals from the electronic circuitry. A physical assembly supports the emulation circuitry and the electronic circuitry as a unit. Other electronic systems and emulation and testing devices, cables, systems and methods are also disclosed.