Patents by Inventor Henry Samueli
Henry Samueli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7512154Abstract: A number of features for enhancing the performance of a wireless communication system, in which data is transmitted between a central node and a plurality of subscriber nodes located remotely with respect to the central node, are presented. The power transmission level, slot timing, and equalization of the subscriber nodes are set by a ranging process. Data is transmitted by the subscriber nodes in fragmented form. Various measures are taken to make transmission from the subscriber nodes robust. The uplink data transmission is controlled to permit multiple access from the subscriber nodes.Type: GrantFiled: October 11, 2006Date of Patent: March 31, 2009Assignee: Broadcom CorporationInventors: Thomas J. Quigley, Jonathan S. Min, Lisa V. Denney, Henry Samueli, Sean F. Nazareth, Feng Chen, Fang Lu, Christopher R. Jones
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Patent number: 7453935Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: March 20, 2007Date of Patent: November 18, 2008Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20080176525Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.Type: ApplicationFiled: March 24, 2008Publication date: July 24, 2008Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli
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Patent number: 7394884Abstract: To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output signal is compared with the bunched pulse train. The selected phase shifted signal is changed responsive to the comparison so the output signal occurs at the average frequency of the bunched pulse train. The oscillator is formed as a plurality of differential amplifier stages having equal controllable delays. The stages are connected together to form a ring oscillator. The output signal is compared with the bunched pulse train through a FIFO. A signal representative of the state of the FIFO is used as an error signal to control the selection of the phase shifted signal to be used as the output signal.Type: GrantFiled: February 27, 2004Date of Patent: July 1, 2008Assignee: Broadcom CorporationInventors: Tarek Kaylani, Fang Lu, Henry Samueli
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Publication number: 20080150632Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: February 26, 2008Publication date: June 26, 2008Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20080151988Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: ApplicationFiled: December 4, 2007Publication date: June 26, 2008Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7369608Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.Type: GrantFiled: August 6, 2004Date of Patent: May 6, 2008Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli
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Publication number: 20080049826Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: ApplicationFiled: August 28, 2007Publication date: February 28, 2008Inventors: Oscar Agazzi, John Creigh, Mehdi Hatamian, David Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7336131Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: May 25, 2006Date of Patent: February 26, 2008Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7321619Abstract: An aspect of the invention provides for recovering communicated information in a communication system. Recovering communicated information in a communication system may include generating a first digital signal from a received analog signal bearing communicated information, the first digital signal having a pre-cursor response and a post-cursor response. A second digital signal may be generated that limits a duration of at least a portion of the post-cursor response and a third digital signal may be generated that inhibits at least a portion of the pre-cursor response. A fourth digital signal that inhibits at least a portion of the post-cursor response and a fifth digital signal that limits a duration of at least a portion of the fourth signal may be generated in order to recover the communicated information. A sixth digital signal based on at least the third digital signal and the fifth digital signal may be generated.Type: GrantFiled: September 30, 2002Date of Patent: January 22, 2008Assignee: Broadcom CorporationInventors: Henry Samueli, Fang Lu, Avanindra Madisetti
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Patent number: 7317772Abstract: Carrier signals modulated by information (video and/or data) signals are received through a cable and are converted to modulated signals at an intermediate frequency. The IF signals are sampled at a particular frequency to produce digital information signals. The digital information signals are introduced to a variable interpolator which produces first digital signals. The first digital signals are introduced to a complex multiplier which produces second digital signals. The second digital signals pass to an adaptive equalizer which selects for each of the second signals in accordance with the amplitude of such second signals, an individual one of a multitude of amplitude levels involved in quadrature amplitude modulation. These selected amplitude levels represent the information (video and/or data). The output signals from the adaptive equalizer are introduced to a first signal recovery loop which includes a first numerically controlled oscillator.Type: GrantFiled: April 23, 2003Date of Patent: January 8, 2008Assignee: Broadcom CorporationInventors: Henry Samueli, Loke K. Tan, Jeffrey S. Putnam
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Patent number: 7305029Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: October 8, 2003Date of Patent: December 4, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7302013Abstract: Digital signal processing for television signals includes digital feedback loops. Analog information signals are oversampled to provide digital signals. The digital signals are introduced to a digital carrier recovery loop and a digital symbol recovery loop. The gain of the digital signals is also regulated in a feedback loop. The digital signals are processed to recover the data in the data signals. The use of digital feedback loops allows information recovered from the digital signals to be precise. Carrier signals can be directly demodulated to produce baseband inphase and quadrature signals, or first downconverted to produce intermediate frequency signals.Type: GrantFiled: December 30, 2003Date of Patent: November 27, 2007Assignee: Broadcom CorporationInventors: Henry Samueli, Alan Y. Kwentus, Thomas D. Kwon
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Publication number: 20070242739Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: ApplicationFiled: March 27, 2007Publication date: October 18, 2007Inventors: Oscar Agazzi, John Creigh, Mehdi Hatamian, David Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7263134Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: August 17, 2004Date of Patent: August 28, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli, David E. Kruse, Arthur Abnous
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Publication number: 20070195875Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: ApplicationFiled: March 20, 2007Publication date: August 23, 2007Inventors: Oscar Agazzi, John Creigh, Mehdi Hatamian, David Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20070183540Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: ApplicationFiled: March 20, 2007Publication date: August 9, 2007Inventors: Oscar Agazzi, John Creigh, Mehdi Hatamian, David Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20070109995Abstract: A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations.Type: ApplicationFiled: October 23, 2006Publication date: May 17, 2007Applicant: Broadcom CorporationInventors: Thomas Quigley, Jonathan Min, Lisa Denney, Henry Samueli, Sean Nazareth, Feng Chen, Fang Lu, Christopher Jones
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Publication number: 20070086484Abstract: A number of features for enhancing the performance of a wireless communication system, in which data is transmitted between a central node and a plurality of subscriber nodes located remotely with respect to the central node, are presented. The power transmission level, slot timing, and equalization of the subscriber nodes are set by a ranging process. Data is transmitted by the subscriber nodes in fragmented form. Various measures are taken to make transmission from the subscriber nodes robust. The uplink data transmission is controlled to permit multiple access from the subscriber nodes.Type: ApplicationFiled: October 11, 2006Publication date: April 19, 2007Applicant: Broadcom CorporationInventors: Thomas Quigley, Jonathan Min, Lisa Denney, Henry Samueli, Sean Nazareth, Feng Chen, Fang Lu, Christopher Jones
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Patent number: 7197069Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: October 8, 2003Date of Patent: March 27, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli