Patents by Inventor Henry T. Nicholas

Henry T. Nicholas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040133668
    Abstract: An end user device is provided that supports a connection to a plurality of data communication networks. The end user device detects which data communication networks are available, and selectively determines which of the plurality of data communication networks provides the most optimal communication channel. The end user device also provides for seamless transitions between different data communication networks, thus permitting all network communication tasks to be performed in a seamless, uninterrupted manner regardless of the location of the device, the type of network connection being used, or the form of data communication being carried out. The end user device further provides for simultaneous communication over a plurality of data communication networks utilizing a single network identity.
    Type: Application
    Filed: September 12, 2003
    Publication date: July 8, 2004
    Applicant: Broadcom Corporation
    Inventor: Henry T. Nicholas
  • Patent number: 5459340
    Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: October 17, 1995
    Assignee: TRW Inc.
    Inventors: James M. Anderson, Andrew R. Coulson, Vincent J. Demaioribus, Henry T. Nicholas
  • Patent number: 5451801
    Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: September 19, 1995
    Assignee: TRW Inc.
    Inventors: James M. Anderson, Andrew R. Coulson, Vincent J. Demaioribus, Henry T. Nicholas
  • Patent number: 5350704
    Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: September 27, 1994
    Assignee: TRW Inc.
    Inventors: James M. Anderson, Andrew R. Coulson, Vincent J. Demaioribus, Henry T. Nicholas
  • Patent number: 5217916
    Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.
    Type: Grant
    Filed: February 4, 1991
    Date of Patent: June 8, 1993
    Assignee: TRW Inc.
    Inventors: James M. Anderson, Andrew R. Coulson, Vincent J. Demaioribus, Henry T. Nicholas