Abstract: A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.

Abstract: A programmable interconnect system includes a two-level hierarchal structure of programmable interconnect chips on a circuit board. The first-level, or "local", interconnect chips are connected to user components. A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.

Abstract: An integrated, user-programmable interconnect architecture, includes a plurality of input/output pads arranged in a matrix of rows and columns, each of the input/output pads being connected to a first one of its row neighbors and a first one of its column neighbors by a two-state programmable interconnect element in series with a first three-state programmable interconnect element having first programming characteristics. A plurality of first conductors is generally disposed in a direction parallel to the rows, each of the rows having at least one of the first conductors connected through ones of the first three-state programmable interconnect elements to selected ones of the input/output pads associated therewith, at least one of the first conductors segmented by at least one of the two-state programmable interconnect elements.

Abstract: An interconnection element for use in an user-configurable interconnection technology includes a normally shorted fuse element and a normally open antifuse element connected in series. The antifuse element is designed to program at a first current at a selected programming voltage. The fuse element is designed to program at a second current which exceeds the first current by a margin sufficient to prevent inadvertent programming of fuse elements during the antifuse element programming cycle. An interconnection network for use in integrated circuits and other connection networks includes a plurality of circuit nodes which may be selectively connected to one another. Each circuit node is connected to other circuit nodes using the interconnection element of the present invention which includes an antifuse element which programs at a programming voltage and a first current in series with a fuse element which programs at a second current having a magnitude larger than the first current.