Patents by Inventor Henry W. Chung

Henry W. Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5571751
    Abstract: A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.
    Type: Grant
    Filed: August 25, 1994
    Date of Patent: November 5, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Henry W. Chung
  • Patent number: 5352622
    Abstract: A self-aligned thin-film ceramic oxide stacked capacitor on an underlying semiconductor substrate using a spin-on ceramic oxide fabricated by forming conductive pillars and the lower electrode, forming a temporary layer, building up the semiconductor substrate around the temporary layer, removing the temporary layer, and then spinning on the ceramic oxide. This results in a ceramic oxide stacked capacitor with the conformal thin-film ceramic oxide encapsulated by the top electrode.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: October 4, 1994
    Assignee: National Semiconductor Corporation
    Inventor: Henry W. Chung
  • Patent number: 5094981
    Abstract: Electrical connections to specified semiconductor or electrically conductive portions (18, 26, and 30) of a structure created from a semiconductive body (10) are created by a process in which a titanium contact layer (34) is deposited on the structure over the specified portions. An electrically conductive barrier material layer (36) which consists principally of non-titanium refractory material is formed over the contact layer. The resulting structure is then annealed at a temperature above 550.degree. C. in order to lower the contact resistance. The anneal is preferably done at 600.degree. C. or more for 10-120 seconds in a gas whose principal constituent is nitrogen. An electrically conductive primary interconnect layer is formed over the barrier material layer after which all three layers are patterned to create a composite interconnect layer.
    Type: Grant
    Filed: April 17, 1990
    Date of Patent: March 10, 1992
    Assignee: North American Philips Corporation, Signetics Div.
    Inventors: Henry W. Chung, Tsui Y. Yao