Patents by Inventor Henry W. Hurst

Henry W. Hurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for creating thick oxide on the bottom surface of a trench structure in silicon
    Patent number: 6861296
    Abstract: A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: March 1, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Henry W. Hurst, James J. Murphy
  • Method for creating thick oxide on the bottom surface of a trench structure in silicon
    Publication number: 20020153557
    Abstract: A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.
    Type: Application
    Filed: June 19, 2002
    Publication date: October 24, 2002
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Henry W. Hurst, James J. Murphy
  • Method for creating thick oxide on the bottom surface of a trench structure in silicon
    Patent number: 6437386
    Abstract: A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: August 20, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Henry W. Hurst, James J. Murphy