Abstract: An apparatus, to be used in a desynchronizer, for minimizing the output jitter of the desynchronizer. The desynchronizer is assumed to include a bit buffer for staging data that is to be output. The desynchronizer is also assumed to include a means for decoding the input signal to determine how justification opportunities in the input signal are used and therefore what justification bits must be leaked by the desynchronizer. The apparatus and method of the present invention uses the information about the incoming justification bits or incoming justification bytes and the state of the buffer to determine the longest possible time to wait before issuing a command to momentarily speed up or delay outputting the next data unit from the bit buffer.

Abstract: A synchronous digital transmission system has network nodes each operating at a respective fixed internal clock rate, each with a justification device for adapting an incoming signal to the respective fixed internal clock rate thereof by positive or negative justification actions, and for controlling a memory device which stores payload bytes of a frame of the incoming signal and outputs the payload bytes at the internal clock rate of a respective network node. The justification device has a first circuit (10) for counting incoming/outgoing frame bytes and calculating at sampling instants (T.sub.i) a difference value (.DELTA..sub.i) and a change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i), has a second circuit (20) for calculating a control value (OFFSET) which is dependent on the change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i) and on a correction factor (LEAK), and has a third circuit (30) for comparing at the sampling instants (T.sub.